A semiconductor device includes a substrate having a plurality of pads on a surface of the substrate, a semiconductor chip that includes a plurality of metal bumps connected to corresponding pads on the substrate, a first resin layer between the surface of the substrate and the semiconductor chip, a second resin layer between the substrate and the semiconductor chip and between the first resin layer and at least one of the metal bumps, and a third resin layer on the substrate and above the semiconductor chip.

A semiconductor device includes a substrate having a plurality of pads on a surface of the substrate, a semiconductor chip that includes a plurality of metal bumps connected to corresponding pads on the substrate, a first resin layer between the surface of the substrate and the semiconductor chip, a second resin layer between the substrate and the semiconductor chip and between the first resin layer and at least one of the metal bumps, and a third resin layer on the substrate and above the semiconductor chip.

Disclosed are semiconductor packages and methods of manufacturing the same. The semiconductor package comprises a substrate, a first unit structure attached to the substrate, and a second unit structure attached to the first unit structure. Each of the first and second unit structures comprises an adhesive layer, a lower semiconductor chip on the adhesive layer, an upper semiconductor chip on and in contact with the lower semiconductor chip, and a plurality of vias penetrating the upper semiconductor chip and connecting with the lower and upper semiconductor chips.

Disclosed are semiconductor packages and methods of manufacturing the same. The semiconductor package comprises a substrate, a first unit structure attached to the substrate, and a second unit structure attached to the first unit structure. Each of the first and second unit structures comprises an adhesive layer, a lower semiconductor chip on the adhesive layer, an upper semiconductor chip on and in contact with the lower semiconductor chip, and a plurality of vias penetrating the upper semiconductor chip and connecting with the lower and upper semiconductor chips.