A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.

A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.

The present invention relates to a substrate for an optical device, which is configured to connect an optical element substrate and an electrode substrate in a fitting manner, and simultaneously, to form one or more bridge pads which are insulated from the optical element substrate by a horizontal insulating layer, on the optical element substrate. The substrate for an optical device according to a first aspect of the present invention comprises: an optical element substrate which is made of a metal plate and contains a plurality of optical elements therein; a pair of electrode substrates which are made of an insulating material to form a conductive layer on at least a portion of the upper surface thereof, are connected to both side surfaces of the optical element substrate, respectively, and are wire-bonded to the electrodes of the optical elements; and a fitting means which is formed on the side surfaces of the electrode substrate and the optical element substrate to fit the optical element substrate and the electrode substrate. The substrate for an optical device according to a second aspect of the present invention comprises: an optical element substrate which is made of a metal plate and contains a plurality of optical elements therein; a pair of electrode substrates which are made of a metal material to be connected to both side surfaces of the optical element substrate, respectively, and are wire-bonded to the electrodes of the optical elements; a fitting means which is formed on the side surfaces of the electrode substrate and the optical element substrate to fit the optical element substrate and the electrode substrate; and a fitting-type vertical insulating layer which is interposed between the optical element substrate and the electrode substrate so as to be connected to the fitting means.

A semiconductor device includes a semiconductor element, a bonding wire that is electrically connected to the semiconductor element, a connection terminal, and sealing material that seals the semiconductor element, the bonding wire, and a part of the connection terminal. In addition, the connection terminal includes a plate-shaped lead part having a bonding area to which the bonding wire is bonded and an anchor part protruding from a first side part of the lead part. In the semiconductor device, since the rear surface of a die pad and the rear surface of the lead part exposed to the outside in a sealing main surface of the sealing material occupy a predetermined area or more, the heat dissipation of the semiconductor device is improved.

A semiconductor device includes a semiconductor element, a bonding wire that is electrically connected to the semiconductor element, a connection terminal, and sealing material that seals the semiconductor element, the bonding wire, and a part of the connection terminal. In addition, the connection terminal includes a plate-shaped lead part having a bonding area to which the bonding wire is bonded and an anchor part protruding from a first side part of the lead part. In the semiconductor device, since the rear surface of a die pad and the rear surface of the lead part exposed to the outside in a sealing main surface of the sealing material occupy a predetermined area or more, the heat dissipation of the semiconductor device is improved.

A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.

A power module substrate 10 is provided with: an insulating substrate 1; and a metal sheet 2 that is joined to the insulating substrate 1 via a brazing material 3, wherein regarding the surface roughness, in the thickness direction, of the lateral surface of the metal sheet 2, the surface roughness of a corner 2a farthest from the center of the metal sheet 2 is larger than the surface roughness of plane parts 2b, which bound the corner, in at least a plan view. Also provided is a power module 100 which is formed by mounting an electronic component 40 on this power module substrate 10.

A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.

A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.