A semiconductor package includes a frame having a first surface, a second surface opposite the first surface, and a through-hole, a first semiconductor chip in the through-hole of the frame, a second semiconductor chip on the frame, a first connection structure on the first surface of the frame and including a first redistribution structure electrically connected to the first semiconductor chip and having a third surface contacting the first surface of the frame, the first redistribution structure including a first redistribution layer and a first redistribution via, a first pad on a center portion of a fourth surface of the first redistribution structure opposite the third surface, a second pad on an edge portion of the fourth surface, a second connection structure on the second surface and comprising a second redistribution structure electrically connected to the second semiconductor chip and including a second redistribution layer and a second redistribution via, and an electrical connection metal on the first pad on the fourth surface, wherein the electrical connection metal is not on the second pad.

A semiconductor package includes a frame having a first surface, a second surface opposite the first surface, and a through-hole, a first semiconductor chip in the through-hole of the frame, a second semiconductor chip on the frame, a first connection structure on the first surface of the frame and including a first redistribution structure electrically connected to the first semiconductor chip and having a third surface contacting the first surface of the frame, the first redistribution structure including a first redistribution layer and a first redistribution via, a first pad on a center portion of a fourth surface of the first redistribution structure opposite the third surface, a second pad on an edge portion of the fourth surface, a second connection structure on the second surface and comprising a second redistribution structure electrically connected to the second semiconductor chip and including a second redistribution layer and a second redistribution via, and an electrical connection metal on the first pad on the fourth surface, wherein the electrical connection metal is not on the second pad.

A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.

A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.

A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in a peripheral portion covered with a protective film. On the other hand, a thickness of a wiring formed in the same step as the pad is larger than that of the pad in the wire bonding portion. The main conductive film of the pad in the wire bonding portion is comprised of only one layer of a first aluminum film, while the main conductive film of the wiring is comprised of at least two layers of aluminum films (the first aluminum film and a second aluminum film) in any region of the wiring.

The present invention relates to a substrate for an optical device, which is configured to connect an optical element substrate and an electrode substrate in a fitting manner, and simultaneously, to form one or more bridge pads which are insulated from the optical element substrate by a horizontal insulating layer, on the optical element substrate. The substrate for an optical device according to a first aspect of the present invention comprises: an optical element substrate which is made of a metal plate and contains a plurality of optical elements therein; a pair of electrode substrates which are made of an insulating material to form a conductive layer on at least a portion of the upper surface thereof, are connected to both side surfaces of the optical element substrate, respectively, and are wire-bonded to the electrodes of the optical elements; and a fitting means which is formed on the side surfaces of the electrode substrate and the optical element substrate to fit the optical element substrate and the electrode substrate. The substrate for an optical device according to a second aspect of the present invention comprises: an optical element substrate which is made of a metal plate and contains a plurality of optical elements therein; a pair of electrode substrates which are made of a metal material to be connected to both side surfaces of the optical element substrate, respectively, and are wire-bonded to the electrodes of the optical elements; a fitting means which is formed on the side surfaces of the electrode substrate and the optical element substrate to fit the optical element substrate and the electrode substrate; and a fitting-type vertical insulating layer which is interposed between the optical element substrate and the electrode substrate so as to be connected to the fitting means.

Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.

A semiconductor device includes a semiconductor element, a bonding wire that is electrically connected to the semiconductor element, a connection terminal, and sealing material that seals the semiconductor element, the bonding wire, and a part of the connection terminal. In addition, the connection terminal includes a plate-shaped lead part having a bonding area to which the bonding wire is bonded and an anchor part protruding from a first side part of the lead part. In the semiconductor device, since the rear surface of a die pad and the rear surface of the lead part exposed to the outside in a sealing main surface of the sealing material occupy a predetermined area or more, the heat dissipation of the semiconductor device is improved.

A semiconductor device includes a semiconductor element, a bonding wire that is electrically connected to the semiconductor element, a connection terminal, and sealing material that seals the semiconductor element, the bonding wire, and a part of the connection terminal. In addition, the connection terminal includes a plate-shaped lead part having a bonding area to which the bonding wire is bonded and an anchor part protruding from a first side part of the lead part. In the semiconductor device, since the rear surface of a die pad and the rear surface of the lead part exposed to the outside in a sealing main surface of the sealing material occupy a predetermined area or more, the heat dissipation of the semiconductor device is improved.

An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 μm, 0.01 to 0.3 μm, and 0.01 to 0.5 μm, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 μm, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.