A semiconductor package includes a first die pad, a first semiconductor die mounted on the first die pad, an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die, a plurality of package leads that each protrude out of a first outer face of the encapsulant body, a connection lug that protrudes out of a second outer face of the encapsulant body, the second outer face being opposite from the first outer face. The first semiconductor die includes first and second voltage blocking terminals. The connection lug is electrically connected to one of the first and second voltage blocking terminals of the first semiconductor die. A first one of the package leads is electrically connected to an opposite one of the first and second voltage blocking terminals of the first semiconductor die that the first connection lug is electrically connected to.

A light emitting element housing package of the present disclosure includes a base part including a first surface including a first recessed part for mounting a light emitting element. Surface roughness Sa of at least such a region of a bottom surface of the first recessed part that is opposite to a light emitting element mounted on the first recessed part is smaller than surface roughness Sa of a region other than the first recessed part of the first surface. Further, a light emitting device of the present disclosure includes the light emitting element housing package and a light emitting element housed in the light emitting element housing package. Further, a light emitting module of the present disclosure includes the light emitting device and a module substrate on which the light emitting device is mounted.

A light emitting element housing package of the present disclosure includes a base part including a first surface including a first recessed part for mounting a light emitting element. Surface roughness Sa of at least such a region of a bottom surface of the first recessed part that is opposite to a light emitting element mounted on the first recessed part is smaller than surface roughness Sa of a region other than the first recessed part of the first surface. Further, a light emitting device of the present disclosure includes the light emitting element housing package and a light emitting element housed in the light emitting element housing package. Further, a light emitting module of the present disclosure includes the light emitting device and a module substrate on which the light emitting device is mounted.

A light emitting diode module includes a first conductive device, a second conductive device, an insulating structure and a plating layer. The first conductive device includes a first metal layer and a first protecting layer covering the first metal layer. The second conductive device includes a second metal layer and a second protecting layer covering the second metal layer. The insulating structure covers around the first and the second conductive devices. The plating layer is disposed on the first and the second protecting layers in a first and a second openings of the insulating structure. The insulating structure covers portions of upper surfaces of the first and the second conductive devices. The plating layer covers remaining portions of the upper surfaces of the first and the second conductive devices. Lower surfaces of the first and the second conductive devices are located in the second opening.

A light emitting diode module includes a first conductive device, a second conductive device, an insulating structure and a plating layer. The first conductive device includes a first metal layer and a first protecting layer covering the first metal layer. The second conductive device includes a second metal layer and a second protecting layer covering the second metal layer. The insulating structure covers around the first and the second conductive devices. The plating layer is disposed on the first and the second protecting layers in a first and a second openings of the insulating structure. The insulating structure covers portions of upper surfaces of the first and the second conductive devices. The plating layer covers remaining portions of the upper surfaces of the first and the second conductive devices. Lower surfaces of the first and the second conductive devices are located in the second opening.

A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.

A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.

A semiconductor structure includes a substrate, a chip, a first edge pad, a first central pad, a second edge pad, and a second central pad. The substrate has a first surface and a conductive trace extending above the substrate. The chip is above the first surface of the substrate, and has a sidewall, a central area, and an edge area. The first edge pad is on the edge area. The first central pad is on the central area and electrically connected to the first edge pad. The second edge pad is on the edge area of the chip. A distance between the first edge pad and the sidewall of the chip is substantially smaller than a distance between the second edge pad and the sidewall of the chip. The second central pad is on the central area of the chip and electrically connected to the second edge pad.

A package includes an integrated circuit that includes at least one active area and at least one secondary device area, a support configured to support the integrated circuit, and a die attach material. The integrated circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.

A package includes an integrated circuit that includes at least one active area and at least one secondary device area, a support configured to support the integrated circuit, and a die attach material. The integrated circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.