A semiconductor package includes a connection substrate on a package substrate and has an opening that penetrates therethrough. A chip stack is on the package substrate and in the opening. A redistribution layer is on the connection substrate and the chip stack. An upper semiconductor chip is on first redistribution pads of the redistribution layer. External terminals are on a bottom surface of the package substrate. The chip stack includes a first semiconductor chip on substrate pads of the package substrate, and a second semiconductor chip on the first semiconductor chip and second redistribution pads of the redistribution layer. The redistribution layer includes a first region that overlaps the upper semiconductor chip and a second region beside the upper semiconductor chip. The first redistribution pads are on the first region. The second redistribution pads are on the second region.

A memory may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a row control circuit. The second wafer may include a second logic structure including a column control circuit.

A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

A semiconductor package includes: a package board including a plurality of connection pads; a semiconductor chip including a first surface and a plurality of bonding pads, wherein the first surface of the semiconductor chip contacts a first surface of the package board, and wherein the plurality of bonding pads are respectively connected to the plurality of connection pads; and a thermal fuse circuit connected between a sensing connection pad of the plurality of connection pads and a sensing bonding pad of the plurality of bonding pads, and configured to open between the sensing connection pad and the sensing bonding pad when an internal temperature of the thermal fuse circuit is greater than or equal to a cutoff temperature of the thermal fuse circuit.

A method and apparatus for wafer bonding. The method includes that, a first position parameter of a first alignment mark on a first wafer is determined by using a optical beam; a second position parameter of a second alignment mark on a second wafer is determined with the optical beam, the optical beam has a property of transmitting through a wafer; a relative position between the first wafer and the second wafer is adjusted with the optical beam according to the first position parameter and the second position parameter until the relative position between the first alignment mark and the second alignment mark satisfies a predetermined bonding condition; and the first wafer is bonded to the second wafer.

A method for manufacturing a semiconductor device of an embodiment, comprises a step of mounting a first semiconductor element on a board and a step of accommodating a member in which a plate-shaped member and a first adhesive layer are stacked in a collet and pressure-bonding the heated first adhesive layer on the board on which the first semiconductor element is mounted. The collet has a member having the first Young's modulus and a second member having a second Young's modulus which is lower than the first Young's modulus on a surface that accommodates the member in which the plate-shaped member and the first adhesive layer are stacked.

A method of manufacturing a semiconductor package may include providing a substrate having first and second cutting regions respectively provided along first and second side portions opposite to each other and a mounting region between the first and second cutting regions is provided, disposing at least one semiconductor chip on the mounting region, forming a molding member on the substrate, and removing a dummy curl portion and at least portions of dummy runner portions from the molding member. The molding member may include a sealing portion, the dummy curl portion provided outside the second side portion of the substrate, and the plurality of dummy runner portions on the second cutting region to connect the sealing portion and the dummy curl portion. The substrate may include adhesion reducing pads in the second cutting region, which may contact the dummy runner portions respectively.

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

According to one embodiment, a semiconductor device includes a board, a first member, a first adhesive layer, a first electronic component, a second electronic component, and a resin. The board includes a first surface. The first member includes a second surface, and a third surface made of a material including a first organic material. The first adhesive layer adheres to the first surface and the second surface. The first electronic component is attached to the first surface, and embedded in the first adhesive layer. The resin in which the first member, the first adhesive layer, and the second electronic component embedded adheres to the first surface and the third surface.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor bonded with the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and a contact structure in the insulating layer. The insulating layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.