A buffered direct injection pixel can be operated such that it is automatically zeroed. The operation includes: during a normal operating mode, controlling a gate voltage of an injection transistor with the output of an amplifier to control a bias of photo-current source, an inverting input of the amplifier being connected to input of the injection transistor through a nulling capacitor; during a nulling operation, closing a first switch to connect the nulling capacitor directly to an output of the amplifier; during the nulling operation, closing a second switch to directly couple the input of the injection transistor to a bias voltage causing the nulling capacitor to store a difference between an output of the amplifier and the bias voltage; and after the nulling operation, providing the voltage stored on the nulling capacitor to the inverting input by opening the first and second switches.

An inverse pseudo fully-differential amplifier having a common-mode feedback control circuit and a method for maintaining a stable output common-mode level are provided. The inverse pseudo fully-differential amplifier includes the pseudo fully-differential operation circuit and a common-mode feedback control circuit. The pseudo fully-differential operation circuit includes inverter amplifiers (2) and (3). The inverter amplifiers (2) and (3) respectively have a first feedback control terminal and a second feedback control terminal. Input terminals of the common-mode feedback control circuit are respectively connected with output terminals of the inverter amplifier (2) and (3), and are configured to detect common-mode output voltages of the inverter amplifier (2) and (3). An output terminal of the common-mode feedback control circuit is connected with the first feedback control terminal and the second feedback control terminal, and is configured to generate common-mode feedback to the inverter amplifiers (2) and (3) to maintain a stable common mode output level.

A driver circuit is provided. The driver circuit includes a first operational amplifier circuit, a second operational amplifier circuit, and at least one power switching circuit is provided. The first operational amplifier circuit receives a first input signal and generates a first output signal according to the first input signal. The second operational amplifier circuit receives a second input signal and generates a second output signal according to the second input signal. The at least one power switching circuit is configured to be coupled to switch a first input stage circuit to one of a first output stage circuit and a second output stage circuit, and the at least one power switching circuit is further coupled to switch a second input stage circuit to the other one of the first output stage circuit and the second output stage circuit.

An amplification interface includes a drain of a first FET connected to a first node, a drain of a second FET connected to a second node, and sources of the first and second FETs connected to a third node. First and second bias-current generators are connected to the first and second nodes. A third FET is connected between the third node and a reference voltage. A regulation circuit drives the gate of the third FET to regulate the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a correction current to the first and/or second node. A differential current integrator has a first and second inputs connected to the second and first nodes. The integrator supplies a voltage representing the integral of the difference between the currents received at the second and first inputs.

A driver circuit is provided. The driver circuit includes a first operational amplifier circuit, a second operational amplifier circuit, and at least one power switching circuit is provided. The first operational amplifier circuit receives a first input signal and generates a first output signal according to the first input signal. The second operational amplifier circuit receives a second input signal and generates a second output signal according to the second input signal. The at least one power switching circuit is configured to be coupled to switch a first input stage circuit to one of a first output stage circuit and a second output stage circuit, and the at least one power switching circuit is further coupled to switch a second input stage circuit to the other one of the first output stage circuit and the second output stage circuit.

A buffered direct injection pixel can be operated such that it is automatically zeroed. The operation includes: during a normal operating mode, controlling a gate voltage of an injection transistor with the output of an amplifier to control a bias of photo-current source, an inverting input of the amplifier being connected to input of the injection transistor through a nulling capacitor; during a nulling operation, closing a first switch to connect the nulling capacitor directly to an output of the amplifier; during the nulling operation, closing a second switch to directly couple the input of the injection transistor to a bias voltage causing the nulling capacitor to store a difference between an output of the amplifier and the bias voltage; and after the nulling operation, providing the voltage stored on the nulling capacitor to the inverting input by opening the first and second switches.

A driver circuit includes a first operational amplifier circuit, a second operational amplifier circuit, and at least one power switching circuit is provided. The first operational amplifier circuit receives a first input signal and generates a first output signal according to the first input signal. The second operational amplifier circuit receives a second input signal and generates a second output signal according to the second input signal. The at least one power switching circuit is coupled to the first operational amplifier circuit and the second operational amplifier circuit, and configured to switch at least one power supply for both the first operational amplifier circuit and the second operational amplifier circuit.

A system includes an operational amplifier which includes a first amplifier input, a second amplifier input and an amplifier output. The system includes a first switch which includes a first terminal and includes a second terminal coupled to the first amplifier input. The system includes a second switch which includes a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input. The system includes a first bias current source coupled between the first amplifier input and a common potential and includes a second bias current source coupled between the first terminal of the first switch and the common potential. The system includes a feedback path between the amplifier output and the first amplifier input.

A driver circuit includes a first operational amplifier circuit, a second operational amplifier circuit, and at least one power switching circuit is provided. The first operational amplifier circuit receives a first input signal and generates a first output signal according to the first input signal. The second operational amplifier circuit receives a second input signal and generates a second output signal according to the second input signal. The at least one power switching circuit is coupled to the first operational amplifier circuit and the second operational amplifier circuit, and configured to switch at least one power supply for both the first operational amplifier circuit and the second operational amplifier circuit.

A driver circuit including a first op-amp, a second op-amp, and a power switching circuit is provided. The first op-amp includes a first input stage circuit for generating a first amplified signal and a first output stage circuit. The second op-amp includes a second input stage circuit for generating a second amplified signal and a second output stage circuit. The power switching circuit includes a first output terminal for outputting one of the first amplified signal and the second amplified signal and a second output terminal for outputting the other of the first amplified signal and the second amplified signal. The power switching circuit is configured to switch a first power supply for both the first input stage circuit and the second input stage circuit between a first supply voltage and a second supply voltage in response to the control signal.