A signal receiver circuit includes a first amplification circuit and an offset compensation circuit. The first amplification circuit generates a first amplified signal and a second amplified signal by amplifying an input signal and a reference voltage. The offset compensation circuit adjusts voltage levels of the first and second amplified signals based on a DC level of the input signal and a voltage level of the reference voltage.

A preamplifier comprises an input stage and a capacitive coupling stage. The input stage is arranged to receive a differential signal from a magnetic resistor which indicates a magnetic field sensed on a magnetic disk of a hard disk drive (HDD) when the preamplifier is powered on from an off state. The capacitive coupling stage has an input arranged to receive the differential signal from the input stage, a filter comprising a first resistor, a second resistor, a first capacitor, a second capacitor, and switches arranged in parallel with respective resistors, where the switches are closed when the preamplifier is powered on from the off state to an on state. A switch control is arranged to determine that an offset of the differential signal has settled and open the switches based on the determination.

A method for improving threshold accuracy in an RFID-device through offset cancellation, and including the steps of providing a comparator including a first and a second amplifiers, providing a current output digital-to-analogue converter, AC-coupling in an RF-signal into the detector circuit, during a first phase, applying a signal based on the RF-signal into the first amplifier while a current of the DAC is set to zero, and applying a current of the DAC into the second amplifier while a signal based on the RF-signal is set to zero, during a second phase, applying the current of the DAC into the first amplifier while the signal based on the RF-signal is set to zero, and applying the signal based on the RF-signal into the second amplifier while the current of the DAC is set to zero.

Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

Single controller automatic calibrating circuits for reducing or canceling offset voltages in operational amplifiers (op-amps) in an instrumentation amplifier are disclosed. An automatic calibrating op-amp system is provided that includes an instrumentation amplifier, which includes a front-end amplifier circuit comprising at least one front-end op-amp and a final-stage amplifier circuit comprising a final-stage op-amp. The op-amp(s) can include auxiliary differential inputs for offset voltage cancellation. The automatic calibrating op-amp system also includes an automatic calibration circuit employing a single controller to generate calibration signals on a calibration output to an auxiliary differential input(s) of an op-amp(s) in the instrumentation amplifier for offset voltage cancellation. The automatic calibration circuit includes a single controller to generate calibration signals to the instrumentation amplifier to reduce or cancel offset voltage, thereby eliminating the need to provide multiple automatic calibration circuits or an automatic calibration circuit employing multiple controllers.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

An amplifier circuit can include an amplifier and a resistor network coupled to the amplifier. The resistor network can include a range resistor coupled in parallel to a resistor string, and one or more switches coupled to the resistor string. The resistor network can be used to calibrate gain and common mode rejection ratio (CMRR) of the amplifier circuit.

A high bandwidth Hall sensor includes a high bandwidth path and a low bandwidth path. The relatively high offset (from sensor offset) of the high bandwidth path is estimated using a relatively low offset generated by the low bandwidth path. The relatively high offset of the high bandwidth path is substantially reduced by combining the output of the high bandwidth path with the output of the low bandwidth path to generate a high bandwidth, low offset output. The offset can be further reduced by including transimpedance amplifiers in the high bandwidth sensors to optimize the frequency response of high bandwidth Hall sensor.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

Disclosed is a system comprising a plurality of operational amplifiers, each operational amplifier having individually adjustable operational parameters, and a trimming circuit. The trimming circuit includes successive approximation register (SAR) logic that determines associated memory values. The trimming circuit changes the adjustable operational parameters of each operation amplifier based on the associated memory values.