Systems and methods for providing adaptive power on reset (POR) signals for use with programmable logic devices (PLDs) and/or other semiconductor devices are disclosed. An example adaptive POR signal generator includes a logic device configured to detect a first supply voltage ramp traversal across a first threshold ramp voltage, detect a second supply voltage ramp traversal across a second threshold ramp voltage, and generate a POR signal based, at least in part, on a nominal operating voltage associated with the power supply and/or the supply voltage and/or on a ramp time associated with the first and second supply voltage ramp traversals. The second threshold ramp voltage is higher than the first threshold ramp voltage and the first and second threshold ramp voltages are lower than the nominal operating voltage.

A programmable logic circuit (10) for controlling an electrical facility, in particular a nuclear facility, includes an operating unit (14). The operating unit includes a plurality of types of functional blocks (FB.sub.1, FB.sub.i, FB.sub.N), two distinct types of functional blocks being suitable for executing at least one distinct function, at least one processing module suitable for receiving at least one sequence (46) of functional block(s) to be executed, and at least one internal memory (38) configured to store at least said sequence (46). The programmable logic circuit (10) includes a single functional block of each type, a given functional block being suitable for being called several times, and an execution module (22) configured to execute the called functional block(s) in series, according to said sequence (46).

A programmable logic circuit (10) for controlling an electrical facility, in particular a nuclear facility, includes an operating unit (14). The operating unit includes a plurality of types of functional blocks (FB.sub.1, FB.sub.i, FB.sub.N), two distinct types of functional blocks being suitable for executing at least one distinct function, at least one processing module suitable for receiving at least one sequence (46) of functional block(s) to be executed, and at least one internal memory (38) configured to store at least said sequence (46). The programmable logic circuit (10) includes a single functional block of each type, a given functional block being suitable for being called several times, and an execution module (22) configured to execute the called functional block(s) in series, according to said sequence (46).

This application relates to apparatus and methods for the multiplication of signals. A multiplication circuit (100) has first and second time-encoding modulators (103a, 103b) configured to receive first and second combined signals (S.sub.C1, S.sub.C2) respectively, and generate respective first and second PWM signals (S.sub.PWM1, S.sub.PWM2), each with a cycle frequency that depends substantially on the square of the value of the input combined signal. The first combined signal (S.sub.C1) corresponds to a sum of a first and second input signals (S.sub.1, S.sub.2) and the second combined signal (S.sub.C2) corresponds to the difference between the first and second input signals (S.sub.1, S.sub.2). First and second time-decoding converters (104a, 104b) receive the first and second PWM signals and provide respective first and count values (D.sub.1, D.sub.2) based on a parameter related to the frequency of the respective first or second PWM signal. A subtractor (105) determine a difference between the first and second count values (D.sub.1, D.sub.2) and provides an output signal (D.sub.OUT) based on this difference.

This application relates to apparatus and methods for the multiplication of signals. A multiplication circuit (100) has first and second time-encoding modulators (103a, 103b) configured to receive first and second combined signals (S.sub.C1, S.sub.C2) respectively, and generate respective first and second PWM signals (S.sub.PWM1, S.sub.PWM2), each with a cycle frequency that depends substantially on the square of the value of the input combined signal. The first combined signal (S.sub.C1) corresponds to a sum of a first and second input signals (S.sub.1, S.sub.2) and the second combined signal (S.sub.C2) corresponds to the difference between the first and second input signals (S.sub.1, S.sub.2). First and second time-decoding converters (104a, 104b) receive the first and second PWM signals and provide respective first and count values (D.sub.1, D.sub.2) based on a parameter related to the frequency of the respective first or second PWM signal. A subtractor (105) determine a difference between the first and second count values (D.sub.1, D.sub.2) and provides an output signal (D.sub.OUT) based on this difference.

Methods and apparatus are described for providing and operating an efficient infrastructure to implement a built-in clock stop and scan dump (CSSD) scheme for fabric blocks, such as block random access memory (BRAM), UltraRAM (URAM), digital signal processing (DSP) blocks, configurable logic elements (CLEs), and the like. This is a very useful feature for system debug and can also be applied for emulation use cases (e.g., FPGA emulation). This scheme can be applied to any tiled architecture that has highly repetitive blocks. The infrastructure may include a DFx controller shared across multiple tiled blocks with some distributed logic in each block, in an effort to minimize or at least reduce area overhead. The infrastructure may also minimize or at least reduce utilization of fabric resources in an effort to ensure the least perturbation of the original design, such that the design issues being debugged can be easily reproduced.

In accordance with various embodiments of the present disclosure, a programmable logic array circuit is provided. In some embodiments, the programmable logic array circuit comprises an AND plane comprising a plurality of groups of product term straps, an OR plane comprising a plurality of output lines, a first plurality of dynamically driven shield lines in the AND plane, and a second plurality of dynamically driven shield lines in the OR plane. Each of the plurality of groups of product term straps is adjacent to only one corresponding one of the first plurality of dynamically driven shield lines. Each of the plurality of output lines is adjacent to only one corresponding one of the second plurality of dynamically driven shield lines.

In accordance with various embodiments of the present disclosure, a programmable logic array circuit is provided. In some embodiments, the programmable logic array circuit comprises an AND plane comprising a plurality of groups of product term straps, an OR plane comprising a plurality of output lines, a first plurality of dynamically driven shield lines in the AND plane, and a second plurality of dynamically driven shield lines in the OR plane. Each of the plurality of groups of product term straps is adjacent to only one corresponding one of the first plurality of dynamically driven shield lines. Each of the plurality of output lines is adjacent to only one corresponding one of the second plurality of dynamically driven shield lines.