A circuit device includes a phase comparison circuit that performs phase comparison between a reference clock signal and a feedback clock signal, a control voltage generation circuit that generates a control voltage, a voltage controlled oscillation circuit that generates a clock signal, a dividing circuit that divides the clock signal and outputs the feedback clock signal, a processing circuit that sets a division ratio of the dividing circuit, a first register in which slope information of a waveform signal for spreading the frequency of the clock signal is set, and a second register in which amplitude information of the waveform signal is set. The processing circuit generates a waveform signal value based on the slope information and the amplitude information set in the first and second registers, and outputs division ratio data based on the waveform signal value and the division ratio setting value to the dividing circuit.

A transmitter and a method capable of transmitting a transmission signal that satisfies a high S/N ratio are provided. A transmitter includes a first signal generation unit including a distributor configured to receive a first N (N: an integer greater than or equal to 3) value digital signal generated from a baseband signal, divide the first N-value digital signal into (N1) binary digital signals, and output the divided (N1) binary digital signals, and a signal amplification unit configured to amplify each of the (N1) binary digital signals and output a transmission signal obtained by combining the amplified (N1) signals.

A digital-to-analog conversion circuit is used for converting a first digital input into a first analog output, and includes a segmentation circuit, a plurality of multi-bit dynamic element matching digital-to-analog converters (DEM DACs), and a combination circuit. The segmentation circuit applies segmentation to the first digital input to generate a plurality of code segments. The multi-bit DEM DACs convert the code segments into a plurality of DAC outputs, respectively, wherein the multi-bit DEM DACs include at least a first multi-bit DEM DAC and a second multi-bit DEM DAC, and the first multi-bit DEM DAC and the second multi-bit DEM DAC employ different DEM techniques. The combination circuit combines the DAC outputs to generate the first analog output.

A system may include a modulator configured to generate a modulated data stream of samples from an input signal wherein each value of data in the modulated data stream when encoded is represented by a multi-bit code, wherein the modulator comprises a quantizer configured to quantize the modulated data stream from the input signal and feed back the modulated data stream as a feedback signal to an input of the modulator and a memory configured to store one or more samples of the modulated data stream. The system may also include an encoder configured to generate a synchronized serialized code stream from the modulated data stream. The quantizer may be configured to, based on the one or more samples of the modulated data stream stored in the memory, constrain the modulated data stream such that a synchronization state of the synchronized serialized code stream generated by the encoder is determinable based on the synchronized serialized code stream.

What is provided is a subtractor, as a re-quantization device, which is configured to detect re-quantization noise, a discrete time filter which is configured to perform frequency weighting on the detected re-quantization noise, an adder which is configured to add an additional signal to quantization noise, and an additional signal selector which is configured to select a value at the present time of a column of an additional signal for minimizing the magnitude of quantization noise having been subjected to frequency weighting evaluated one sampling or more later.

A digital delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a multi-bit quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter. The multi-bit quantizer may further be configured to operate in at least two modes comprising: (a) a normal mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a set of a plurality of quantization levels; and (b) a code suppression mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a subset of the set of a plurality of quantization levels.

The disclosure relates to a microphone assembly including a multibit analog-to-digital converter configured to generate N-bit samples representative of a microphone signal. The microphone assembly also includes a first digital-to-digital converter configured to generate a corresponding M-bit digital signal based on N-bit digital samples, wherein N and M are positive integers and N>M. The microphone assembly may include a data interface configured to repeatedly receive samples of the M-bit digital signal and write bits of the M-bit digital signal to a data frame.

Provided is a circuit device including: a phase comparison circuit that performs phase comparison between a reference clock signal and a feedback clock signal; a control voltage generation circuit that generates a control voltage; a voltage controlled oscillation circuit that generates a clock signal; a dividing circuit that divides the clock signal and outputs the feedback clock signal; a processing circuit that sets a division ratio of the dividing circuit; a first register in which slope information of a waveform signal for spreading the frequency of the clock signal is set; and a second register in which amplitude information of the waveform signal is set. The processing circuit generates a waveform signal value of the waveform signal based on the slope information and the amplitude information set in the first and second registers, and outputs division ratio data based on the waveform signal value and the division ratio setting value to the dividing circuit.

An apparatus for dynamic range enhancement (DRE) which receives an input signal and provides a DRE output signal is presented. The apparatus has an error correction circuit to apply an error correction factor to the input signal such that the DRE output signal provided by the apparatus is dependent on the input signal and the error correction factor. The error correction factor is representative of an error generated by the apparatus.

The present disclosure provides a converting module formed in a first die. The first die is coupled to a bus having a bus bit width. The converting module includes an analog-to-digital converter, configured to generate a first digital signal having a first bit width different from the bus bit width; and a sigma-delta modulator, coupled to the analog-to-digital converter, and configured to generate a second digital signal according to the first digital signal. The second digital signal has a bit width equal to the bus bit width. The sigma-delta modulator includes a filter and a quantizer. The number of bits outputted by the quantizer is equal to the bus bit width.