H03M13/1162

Parity interleaving apparatus for encoding variable-length signaling information and parity interleaving method using same

A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

METHODS AND APPARATUSES FOR GENERATING OPTIMIZED LDPC CODES

Methods and apparatuses for generating optimized LDPC codes are proposed. One of the methods is a method for generating an optimized LDPC code for an asymmetric transmission channel. The method includes receiving an initial LDPC code for the asymmetric transmission channel. Further, the method includes performing a density evolution threshold optimization for the initial LDPC code in order to obtain the optimized LDPC code for the asymmetric transmission channel. A uniformly mixed symmetric channel density for the asymmetric transmission channel is used in the density evolution threshold optimization.

LDPC DECODER, OPERATING METHOD OF LDPC DECODER, AND SEMICONDUCTOR MEMORY SYSTEM
20210250045 · 2021-08-12 ·

A method for operating a Low Density Parity Check (LDPC) decoder includes assigning each symbol of a codeword as a variable node value for each of a plurality of variable nodes, performing syndrome checking on each check node based on a parity check matrix, calculating flipping function values of the variable nodes based on syndrome values of check nodes and a flipping function, dividing the flipping function values into a plurality of groups, determining a flipping function threshold value based on a group maximum value of a group among the groups, and selectively flipping a variable node value based on a comparison result of a flipping function value of corresponding variable node and the determined flipping function threshold value.

Method, system, device and storage medium for constructing base matrix of PBRL LDPC code
11848684 · 2023-12-19 · ·

The present disclosure relates to a method, system, and non-transitory computer-readable storage medium for constructing a base matrix of a PBRL LDPC code, comprising: determining at least one candidate sub-matrix of a PBRL LDPC code based on a base matrix of a QR-QC-LDPC code; obtaining at least one count of cycles with at least one preset length for each of the at least one candidate sub-matrix; and determining a first sub-matrix of the base matrix of the PBRL LDPC code based on the at least one count of cycles.

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
20230412193 · 2023-12-21 ·

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes.

In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

Data transmission method, data sending device, and data receiving device

A data transmission method, a data sending device, and a data receiving device are provided. The method includes: encoding, by a data sending device, information data by using a low-density parity-check (LDPC) code matrix, to obtain a bit sequence, where the bit sequence includes a first bit sequence, and the first bit sequence includes at least one information bit in the bit sequence; interleaving, the first bit sequence to obtain a first interleaved bit sequence; performing, modulation based on the first interleaved bit sequence to obtain a sending signal, and sending the sending signal. The method also includes: demodulating, by a data receiving device, a receiving signal to obtain a soft value sequence; and de-interleaving, the soft value sequence, to obtain a soft value sequence of a first bit sequence. This can improve a capability of an LDPC code resisting burst interference.

Error correction coded binary array
10931315 · 2021-02-23 · ·

A system and method for detecting an angle of arrival (AoA) of incident waves are disclosed. An array of wave sensors each transduce incident waves into an electrical signal, which is then provided an additional phase shift that varies between sensors. Electrical signals from adjacent wave sensors, having different phase shifts, are coupled via a phase detector to classify the incident waves into zero and one AoA regions for that sensor pair. The outputs from many such phase detectors are combined to divide the space facing the array into many subregions, each subregion being associated with a unique codeword. Incident waves cause detection of codewords, that are decoded according to error detection and correction techniques, such as selecting, from a list, the codeword having a minimum Hamming distance to a received codeword. The decoder then outputs data indicating an AoA subregion associated with the decoded codeword.

PARITY INTERLEAVING APPARATUS FOR ENCODING VARIABLE-LENGTH SIGNALING INFORMATION AND PARITY INTERLEAVING METHOD USING SAME

A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

Parity interleaving apparatus for encoding variable-length signaling information and parity interleaving method using same

A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

Method and apparatus for deciding decoding order for shuffled decoding of LDPC codes

The method for shuffled decoding of LDPC codes includes calculating check-variable mutual information which is mutual information of a message propagating from a plurality of check nodes to a plurality of variable nodes by a check-variable mutual information calculating unit, calculating variable-check mutual information which is mutual information of a message propagating from the plurality of variable nodes to the plurality of check nodes connected to the plurality of variable nodes based on the check-variable mutual information by a variable-check mutual information calculating unit, and Calculating the entire mutual information which is a sum of variable-check mutual information for each of the plurality of variable nodes and determines an operation order of a variable node having the largest entire mutual information among the plurality of variable nodes to be next, by an operation order determining unit.