Patent classifications
H03M13/1162
DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes.
In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.
Data processing device and data processing method
The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.
METHOD AND DEVICE OF SELECTING BASE GRAPH OF LOW-DENSITY PARITY-CHECK CODE
A method and a device of selecting a base graph of a low-density parity-check code are provided. The method includes: acquiring a data information length and a channel coding rate of to-be-encoded data; determining a target base graph selection strategy according to the data information length and an information length range of a base graph; determining a target base graph for the to-be-encoded data according to the target base graph selection strategy and the channel coding rate.
QC-LDPC codes
An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.
Method for generating parity check matrix for low density parity check coding
A method and system for offset lifting is provided. In an embodiment, a method for encoding data includes receiving a K-bit source word input. The method also includes encoding the K-bit source word input according to a LDPC code, a lifting function, and a circulant size offset to generate an N-bit code word output. The circulant size and lifting function are determined according to an information length, a code rate, and a decoder. The method also includes storing the N-bit code word output in input/output memory.
Systems and methods for decoding quasi-cyclic (QC) low-density parity-check (LDPC) codes
A decoder circuit includes an input configured to receive an encoded message generated based on a QC-LDPC code. A first layer process unit is configured to process a first layer of a parity check matrix to generate a plurality of log-likelihood ratio (LLR) values corresponding to a plurality of variable nodes associated with the encoded message respectively. The first layer process unit includes a plurality of row process units configured to process a first plurality of rows of the first layer in parallel to generate a plurality of row update values. A layer update unit is configured to generate a first LLR value for a first variable node using first and second row update values for the first variable node. An output is configured to provide a decoded message generated based the plurality of LLR values.
ERROR CORRECTION CODED BINARY ARRAY
A system and method for detecting an angle of arrival (AoA) of incident waves are disclosed. An array of wave sensors each transduce incident waves into an electrical signal, which is then provided an additional phase shift that varies between sensors. Electrical signals from adjacent wave sensors, having different phase shifts, are coupled via a phase detector to classify the incident waves into zero and one AoA regions for that sensor pair. The outputs from many such phase detectors are combined to divide the space facing the array into many subregions, each subregion being associated with a unique codeword. Incident waves cause detection of codewords, that are decoded according to error detection and correction techniques, such as selecting, from a list, the codeword having a minimum Hamming distance to a received codeword. The decoder then outputs data indicating an AoA subregion associated with the decoded codeword.
DATA TRANSMISSION METHOD, DATA SENDING DEVICE, AND DATA RECEIVING DEVICE
A data transmission method, a data sending device, and a data receiving device are provided. The method includes: encoding, by a data sending device, information data by using a low-density parity-check (LDPC) code matrix, to obtain a bit sequence, where the bit sequence includes a first bit sequence, and the first bit sequence includes at least one information bit in the bit sequence; interleaving, the first bit sequence to obtain a first interleaved bit sequence; performing, modulation based on the first interleaved bit sequence to obtain a sending signal, and sending the sending signal. The method also includes: demodulating, by a data receiving device, a receiving signal to obtain a soft value sequence; and de-interleaving, the soft value sequence, to obtain a soft value sequence of a first bit sequence. This can improve a capability of an LDPC code resisting burst interference.
Low-complexity LDPC encoder
Techniques are described for encoding information data bits using a low-density parity-check matrix optimized for a Low-Density Parity-Check (LDPC) encoder. In an example, the parity-check matrix includes a first matrix and a second matrix. The second matrix is a square matrix, and is also a block diagonal matrix that includes a set of square submatrices located on the diagonal of the block diagonal matrix. An intermediate vector is generated based on the information data bits and the first matrix, and a parity vector of a codeword is generated based on the intermediate vector and the second matrix.
PARITY INTERLEAVING APPARATUS FOR ENCODING VARIABLE-LENGTH SIGNALING INFORMATION AND PARITY INTERLEAVING METHOD USING SAME
A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.