A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

A method and system for offset lifting is provided. In an embodiment, a method for encoding data includes receiving a K-bit source word input. The method also includes encoding the K-bit source word input according to a LDPC code, a lifting function, and a circulant size offset to generate an N-bit code word output. The circulant size and lifting function are determined according to an information length, a code rate, and a decoder. The method also includes storing the N-bit code word output in input/output memory.

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes, in group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bit. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence, the present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

A method of operating a memory system includes receiving information data corresponding to a second program unit that is a part of a first program unit and a write request for the information data from a host; generating a codeword by performing error correction code (ECC) encoding on the received information data such that a partial parity bit corresponding to the information data among all parity bits of the codeword is updated; and providing a memory device with the generated codeword and a write command regarding the codeword.

A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes.

In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

The disclosure generally relates to improvements of a log-likelihood ratios (LLRs) memory structure and memory capacity of a decoding hardware (also referred to as a decoder) in decoding a sequence of codewords encoded with a low-density parity-check (LDPC) code (e.g. a quasi-cyclic (QC) LDPC code). Further, the disclosure relates to the optimization of a processing schedule of a parity check matrix (PCM) describing the LDPC code so as to reduce or minimize the number of patch LLRs that need to be (simultaneously) stored in an LLR memory of a decoder.

A first memory location stores circulant contents of portions A, C, E, and B of a parity check matrix H. A second memory location stores circulant column counts of the portions A, C, E, and B. A third memory location stores a dense matrix equal to (ET.sup.1B+D).sup.1, where T is an identity matrix and D and T are also portions of the parity check matrix H. First and second parity information is generated in response to receiving information data. Generating the first and second parity information includes accessing the circular content of the portions A, C, E, and B of a parity check matrix H and accessing the circulant column counts of the portions A, C, E, and B.

The disclosure generally relates to improvements of a log-likelihood ratios (LLRs) memory structure and memory capacity of a decoding hardware (also referred to as a decoder) in decoding a sequence of codewords encoded with a low-density parity-check (LDPC) code (e.g. a quasi-cyclic (QC) LDPC code). Further, the disclosure relates to the optimization of a processing schedule of a parity check matrix (PCM) describing the LDPC code so as to reduce or minimize the number of patch LLRs that need to be (simultaneously) stored in an LLR memory of a decoder.

A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.