An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.

A method for performing low density parity check (LDPC) coding of a transmitter in a wireless communication system, according to the present disclosure, may comprise the steps of: acquiring a proto-matrix corresponding to a protograph; on the basis of weights and lifting factors of columns of the proto-matrix, acquiring one or more permuted vectors corresponding to each of the columns, a first permuted vector included in the one or more permuted vectors having been randomly generated; distributing the one or more permuted vectors for each row of a corresponding column; on the basis of the distributed one or more permuted vectors, acquiring a plurality of lifted sub matrices corresponding to a plurality of elements of the proto-matrix; generating a base graph on the basis of the plurality of lifted sub matrices; generating a parity check matrix (PCM) on the basis of the base graph; and performing LDPC coding by using the PCM.

[Problem] Encoding and decoding techniques capable of speeding up an error-correction decoding process utilizing channel polarization are provided. [Solution] In an encoding device, the information bit sequence is input on division for each designated bit length; error-correction encoding is performed on an information block of the designated bit length to generate L M-bit codes, each M-bit code having a predetermined bit length M; the L M-bit codes are converted into M L-bit blocks each having a predetermined bit length of L; the M L-bit blocks are Polar-converted to M L-bit codes, each L-bit code having a bit length of L, through channel polarization processing; and division of the information bit sequence is determined based on channel polarization information.

Methods, systems, and devices for wireless communications are described. A wireless communication system may support techniques for correlation-based hardware sequences for layered decoding. In some cases, a user equipment (UE) may partition layers of a submatrix associated with a parity check decoding procedure into a first set of layers and a second set of layers. The UE may sort each set of layers into a respective set of layer orders (e.g., a first set of layer orders and a second set of layer orders) based on an associated set of correlation values. The UE may combine the first set of layer orders and the second set of layer orders to obtain a set of combined layer orders and may select a decoding schedule from a set of decoding schedules used for decoding each of the combined layer orders based on respective schedule lengths for the set of decoding schedules.

Provided is an information processing method. The method includes that: first data to be decoded and one or more decoding parameters of the first data are obtained; a basis matrix is determined based on the one or more decoding parameters; a decoding instruction set including a plurality of decoding instructions is determined based on the basis matrix, wherein the plurality of decoding instructions include elements in the basis matrix; and the first data is decoded based on the decoding instruction set. Further provided are an information processing device and a computer storage medium.

A quasi-cyclic LDPC coding and decoding method and apparatus, and an LDPC coder and decoder. The method includes: determining from a mother basis matrix set a basis matrix used for low density parity check (LDPC) coding (S202), wherein the basis matrix used for LDPC coding includes a first-type element and a second-type element, the first-type element corresponds to an all-zero square matrix, the second-type element corresponds to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and dimensions of the all-zero square matrix and the unit matrix are equal; and performing LDPC coding on an information sequence to be coded according to the basis matrix used for LDPC coding, and/or performing LDPC decoding on a data sequence to be decoded according to the basis matrix used for LDPC coding (S204).

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

A computer-implemented method includes: receiving a code word sequence whose digit quantity is n; determining a check matrix of an order m×n, where a base matrix of the check matrix is a matrix of an order m.sub.b×n.sub.b; setting L variable nodes based on the base matrix, where L is greater than or equal to a quantity of values not equal to 1 in a row with a maximum quantity of values not equal to −1 in the base matrix; separately mapping valid submatrices in each layer of a check node to the L variable nodes; sending, to each of the L variable nodes that were mapped, data corresponding to each valid submatrix in each layer of the check matrix; and performing a corresponding operation in a layered normalized min-sum decoding algorithm by the L variable nodes using the data that was sent.

Estimation of read parameters for a read channel of a solid-state storage device using a machine learning apparatus. The machine learning apparatus may be provided with signal count metrics from multiple regions of the memory cell signal space and syndrome weights from an error correction code. Other inputs may also be provided comprising metrics of the memory or read operations. In an example, the read parameters may include one or more reference threshold voltage values for read voltages applied to a memory cell and/or log-likelihood ratio (LLR) values for the memory cell.

Estimation of read parameters for a read channel of a solid-state storage device using a machine learning apparatus. The machine learning apparatus may be provided with signal count metrics from multiple regions of the memory cell signal space and syndrome weights from an error correction code. Other inputs may also be provided comprising metrics of the memory or read operations. In an example, the read parameters may include one or more reference threshold voltage values for read voltages applied to a memory cell and/or log-likelihood ratio (LLR) values for the memory cell.