This application relates to communicating information between communication devices. A channel coding method is disclosed. A communication device obtains an input sequence of K bits. The communication device encodes the input sequence using a low density parity check (LDPC) matrix H, to obtain an encoded sequence. The LDPC matrix H is determined according to a base matrix and a lifting factor Z. The base matrix includes m rows and n columns, m is greater than or equal to 5, and n is greater than or equal to 27. The lifting factor Z satisfies a relationship of 22*Z≥K. According to the encoding method provided in the embodiments, information bit sequences of a plurality of lengths can be encoded for transmission between the communication devices.

A system and method for allocating network resources are disclosed herein. In one embodiment, the system and method are configured to perform: determining a redundancy version and a new data indicator indicated by control information; determining a base graph of a low density parity check code based on which of a plurality of predefined conditions the redundancy version, and/or the new data indicator satisfy; and sending a signal comprising information bits that are encoded based on the determined base graph of the low density parity check code.

A channel encoding method in a communication or broadcasting system is provided. The channel encoding method includes reading a first sequence corresponding to a parity check matrix, converting the first sequence to a second sequence by applying a certain rule to a block size corresponding to a parity check matrix and the first sequence, and encoding information bits based on the second sequence. The block size has at least two different integer values.

A method for transmitting an information block on the basis of a low density parity check (LDPC) code in a wireless communication system, according to the present disclosure, may comprise: encoding an information block on the basis of a LDPC basegraph H_BG including [MATRIX]; and transmitting the encoded information block. Each element of H_BG is either zero (“0”) or one (“1”), and each element which is “0”, among the elements of H_BG, may represent a Z×Z zero matrix, and each element which is “1”, among the elements of H_BG, may represent a Z×Z matrix acquired on the basis of a circular permutation matrix acquired by circularly shifting a Z×Z identity matrix to the left or right. The submatrix T_BG of H_BG may be a dual diagonal matrix, and the submatrix D_BG of H_BG may be a dual diagonal matrix. The encoding of the information block on the basis of H_BG may comprise encoding the information block on the basis of a parity check matrix (PCM) H which corresponds to H_BG.

Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).