Disclosed are an apparatus and a method for LDPC encoding suitable for highly reliable and low latency communication. The disclosed apparatus comprises: a second inner encoding module for outputting parity bits by means of single parity calculations and accumulation device calculations using bit strings outputted from a first inner encoding module; and the first inner encoding module for outputting a part of the parity bits by means of single parity check calculations for the bits output from a second outer module, and for outputting rest of the parity bit strings by means of single parity check calculations and accumulation device calculations, with a part of the parity bits output by the second inner encoding module as an additional input.

In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises a transmitter that transmits a signal, a communication channel that transports the signal, and a receiver that receives the signal. The transmitter can comprise a pulse-shaping filter that intentionally introduces memory into the signal, and an error control code encoder that is a low-density parity-check (LDPC) error control code encoder. The error control encoder comprises code that is optimized based on the intentionally introduced memory into the signal, a code rate, a signal-to-noise ratio, and an equalizer structure in the receiver. In some embodiments, the communication system is bandwidth constrained, and the transmitted signal comprises an information rate that is higher than for an equivalent system without intentional introduction of the memory at the transmitter.

Memory controllers, decoders and methods to perform decoding of user bits and parity bits including those corresponding to low degree variable nodes. For each of the user bits, the decoder performs a variable node update operation and a check node update operation for connected check nodes. After all of the user bits are processed, the decoder performs a parity node update operation for the parity bits using results of the variable node and check node update operations performed on the user bits.

The technology relates to bandwidth constrained communication systems with neural network based detection. In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises: a transmitter comprising an error control code encoder, a pulse-shaping filter, and a first interleaver; a communication channel; and a receiver comprising a neural network processing block that processes a received signal. The error control code encoder can append redundant information onto the signal. The pulse-shaping filter can intentionally introduce memory into the signal in the form of inter-symbol interference. The first interleaver can change a temporal order of the symbols in the signal. The error control code encoder can be a low-density parity-check (LDPC) error control code encoder. The neural network can be trained with positive mappings between transmitted and decoded training signals, or negative mappings between training signals and a null space of an LDPC generation matrix.

Disclosed are an apparatus and a method for LDPC encoding suitable for highly reliable and low latency communication. The disclosed apparatus comprises: a second inner encoding module for outputting parity bits by means of single parity calculations and accumulation device calculations using bit strings outputted from a first inner encoding module; and the first inner encoding module for outputting a part of the parity bits by means of single parity check calculations for the bits output from a second outer module, and for outputting rest of the parity bit strings by means of single parity check calculations and accumulation device calculations, with a part of the parity bits output by the second inner encoding module as an additional input.

The technology relates to bandwidth constrained communication systems with neural network based detection. In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises: a transmitter comprising an error control code encoder, a pulse-shaping filter, and a first interleaver; a communication channel; and a receiver comprising a neural network processing block that processes a received signal. The error control code encoder can append redundant information onto the signal. The pulse-shaping filter can intentionally introduce memory into the signal in the form of inter-symbol interference. The first interleaver can change a temporal order of the symbols in the signal. The neural network can be trained with positive mappings between transmitted and decoded training signals, or negative mappings between training signals and erroneous decoded signals that are known to contain errors.

The present disclosure provides techniques for bandwidth constrained communication systems with frequency domain information processing. A bandwidth constrained equalized transport (BCET) communication system can include a transmitter, a communication channel, and a receiver. The transmitter can include a pulse-shaping filter that intentionally introduces memory into a signal in the form of inter-symbol interference, an error control code (ECC) encoder, a multidimensional fast Fourier transform (FFT) processing block that processes the signal in the frequency domain, and a first interleaver. The receiver can include an information-retrieving equalizer, a deinterleaver with an ECC decoder, and a second interleaver joined in an iterative ECC decoding loop.

A method in a network node comprises generating a parity-check matrix for decoding a transmission scheme. The transmission scheme comprises a repetition code, an interleaver, and a modulation having a memory property. The parity-check matrix comprises a function of: a differentiator matrix, the differentiator matrix comprising an inverse of an accumulator matrix; a deinterleaver matrix, the deinterleaver matrix comprising an inverse of an interleaver matrix, the interleaver matrix comprising a square unitary permutation matrix for introducing randomness; and a repetition decoder matrix.

An encoding apparatus which performs encoding such as Low Density Parity Check (LDPC) encoding is provided. The encoding apparatus includes: an encoder encoding input bits using a parity check matrix including a plurality of blocks, each being formed of a first information word sub-matrix and a first parity sub-matrix arranged next to each other, and a second information sub-matrix and a second parity sub-matrix arranged next to each other; a bit determiner determining a value of a last sub-parity bit among sub-parity bits generated by encoding the input bits with respect to a first block among the plurality of blocks; and a bit modifier reversing values of bits generated by encoding the input bits with respect to a second block next to the first block based on the value of the last parity bit among the sub-parity bits generated by the encoding with respect to the first block.

A first memory location stores circulant contents of portions A, C, E, and B of a parity check matrix H. A second memory location stores circulant column counts of the portions A, C, E, and B. A third memory location stores a dense matrix equal to (ET.sup.1B+D).sup.1, where T is an identity matrix and D and T are also portions of the parity check matrix H. First and second parity information is generated in response to receiving information data. Generating the first and second parity information includes accessing the circular content of the portions A, C, E, and B of a parity check matrix H and accessing the circulant column counts of the portions A, C, E, and B.