An application specific integrated circuit (ASIC) tangibly encodes a method for fast polynomial updates in fast Chase decoding of binary Bose-Chaudhuri-Hocquenghem (BCH) codes. The method includes the steps of using outputs of a syndrome-based hard-decision (HD) algorithm to find a Groebner basis for a solution module of a modified key equation, upon failure of HD decoding of a BCH codeword received by the ASIC from a communication channel; evaluating polynomials obtained from said Groebner basis at inverses of specified weak-bit locations; and transforming a Groebner basis for a set of flipped weak-bit locations (.sub.1, . . . , .sub.r1) to a Groebner basis for (.sub.1, . . . , .sub.r), wherein .sub.r is a next weak-bit location, wherein r is a difference between a number of errors and a HD correction radius of the BCH codeword.

An error correction code (ECC) decoder includes a finite state machine (FSM) controller and a shared logic circuit. The FSM controller generates a first control signal and a second control signal each corresponding to a certain state. The shared logic circuit includes a plurality of shared Galois field (GF) multipliers, a plurality of shared XOR arithmetic elements, and a plurality of shared multiplexers (MUXs), which are used for an operation selected between a syndrome operation, an error location polynomial operation, an error location operation and an error correction operation, in response to the first and second control signals.

An error correction circuit includes a syndrome calculator suitable for generating syndromes from an n-bit codeword for a single unit of time, an error location polynomial calculator suitable for generating error location polynomial coefficients based on the syndromes provided for the single unit of time, an error location calculator suitable for calculating error locations based on the error location polynomial coefficients for the single unit of time, and an error corrector suitable for correcting errors of the codeword based on the error locations for the single unit of time. The error correction circuit operates in a pipelining manner.

At least one example embodiment discloses a method of soft-decision Wu decoding a code. The code is one of a generalized Reed-Solomon type and an alternant type. The method includes obtaining a module of the code. The module is a sub-module of at least a first extension module and a second extension module. The first extension module is defined by a set of first type constraints and the second extension module is defined by a set of second type constraints. The first type constraints are applicable to a first interpolation algorithm and a second interpolation algorithm and the second type constraints are applicable to the first interpolation algorithm. The method further includes determining a basis for the first extension module and converting the basis for the first extension module to a basis for the module.

A method of operation of a decoder includes receiving first data at the decoder. The method further includes generating second data at the decoder based on the first data. The second data is generated by adjusting an error locator polynomial based on an error parity of the first data.

A decoder configured to decode a representation of the codeword includes an error locator polynomial generator circuit. The error locator polynomial circuit is configured to generate an error locator polynomial based on a decode operation that includes iteratively adjusting values of a first polynomial, a second polynomial, a third polynomial, and a fourth polynomial. The error locator polynomial circuit is also configured to initialize the third polynomial based on even-indexed coefficients of a syndrome polynomial and initialize the fourth polynomial based on odd-indexed coefficients of the syndrome polynomial.

Provided is a memory system comprising an error correction code (ECC) decoder configured to receive data from a memory. The ECC decoder includes a syndrome generator configured to calculate at least one of syndrome vector and an erasure value, the calculation being devoid of erasure location information and an error-location polynomial generator configured to determine error location and error/erasure value polynomials responsive to syndrome and erasure calculation values output from the syndrome generator. An error value generator confirms error values at one or more known error locations based upon the determined error/erasure value polynomials, and an error location generator search for an error evaluation value to confirm the known error locations based upon the determined error location polynomials. Outputs of the error value generator and the error location generator are combined to produce corrected data.

Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.

A decoder includes an error locator polynomial generator circuit configured to determine, during a first cycle of a clock signal, a first value of a parameter. The first value of the parameter is associated with a first iteration of a decode operation and is based on a value of an error locator polynomial associated with a prior iteration of the decode operation. The error locator polynomial generator circuit is further configured to determine, during a second cycle of the clock signal that sequentially follows the first cycle or during a third cycle of the clock signal that sequentially follows the second cycle, an adjusted value of the error locator polynomial. The adjusted value of the error locator polynomial is associated with a second iteration of the decode operation and is based on the first value of the parameter.

Systems, devices, and methods for decoding information bits obtained from storage, including obtaining a codeword from among a plurality of codewords stored in a storage device, wherein the codeword includes a plurality of frames; obtaining an initial error locator polynomial (ELP) corresponding to the codeword; decoding a frame of the plurality of frames; based on determining that the frame is successfully decoded, determine an updated ELP based on the initial ELP and information about the frame; and obtaining information bits corresponding to the codeword based on the updated ELP, wherein the updated ELP includes a plurality of updated coefficients, and wherein the updated ELP is determined by simultaneously calculating at least two updated coefficients from among the plurality of updated coefficients.