A system for time aligning widely frequency spaced signals includes a digital predistortion (DPD) processor and a power amplifier coupled to the DPD processor and operable to provide a transmit signal at a power amplifier output. The system also includes a feedback loop coupled to the power amplifier output. The feedback loop comprises an adaptive fractional delay filter, a delay estimator coupled to the adaptive fractional delay filter, and a DPD coefficient estimator coupled to the delay estimator.

A decision feedback equalizer (DFE) comprises four charge-steering (CS) primary latches and four primary taps. Two of the four CS primary latches are driven by complementary in-phase quarter-rate clocks and the other two of the four CS primary latches are driven by complementary quadrature quarter-rate clocks. No element of the DFE is driven by any half-rate clocks. In some implementations, each of the primary latches including a respective differential pair of n-channel output transistors and each primary tap includes a respective differential pair of p-channel input transistors connected via their gate nodes to a respective one of the four CS primary latches. In other implementations, each of the primary latches including a respective differential pair of p-channel input transistors and each primary tap includes a respective differential pair of n-channel output transistors connected via their gate nodes to a respective one of the four CS primary latches.

A decision feedback equalizer (DFE) comprises two charge-steering (CS) input latches driven by complementary -rate clocks, two pairs of CS primary latches, and two pairs of taps. The primary latches are driven by -rate clocks. In a first aspect, each one of the input latches and the primary latches includes a respective differential pair of n-channel output transistors, and each tap includes a respective differential pair of p-channel input transistors. In a second aspect, each one of the input latches and the primary latches includes a respective differential pair of p-channel input transistors, and each tap includes a respective differential pair of n-channel output transistors. In some implementations, no element of any one of the taps is driven by any -rate clock. In some implementations, every switch of at least one of the taps is driven by one of the -rate clocks.

A reception device for receiving a data signal representing a data value 0 or 1. The reception device includes an equalizer circuit and a control circuit. The equalizer circuit outputs an output value representing a result obtained by comparing a voltage based on the received data signal and a first voltage as a reference, at each clock timing corresponding to the data signal. The control circuit is connected to the equalizer circuit. The control circuit changes, before the data signal is received, a tap coefficient related to a characteristic of the equalizer circuit in a state in which a second voltage different from the first voltage, instead of the voltage of the data signal, is supplied to the equalizer circuit, to detect an inverted tap coefficient that is the tap coefficient at a boundary where a data value of the output value is inverted. The control circuit sets the inverted tap coefficient to the equalizer circuit at a time of receiving the data signal.

A system for receiving signals transmitted via serial links includes an equalizer for accessing a digitized communications signal and producing an equalized output signal, and a fast equalization module for determining output data corresponding to the communications signal. The fast equalization module includes a filter to access an output of the equalizer, a slicer module to access an output of the filter and produce a data output corresponding to the communications signal, a lookup table to provide filtering coefficients to the filter, and a coefficient improvement module to improve the coefficients based on an error signal from the filter. The coefficient improvement module is configured to update the coefficients in the lookup table.

A signal receiver circuit may include: a receiver suitable for generating a received signal based on comparison of an input signal with a reference voltage during a normal operation and based on comparison of the input signal with a target voltage during a training operation; a compensator suitable for applying a weight to the received signal to compensate for the input signal; and a weight adjuster suitable for adjusting the weight based on a level of the received signal during the training operation, wherein during the training operation, the input signal toggles between first and second levels, and the receiver is enabled when the input signal is at the first level.

A system for time aligning widely frequency spaced signals includes a digital predistortion (DPD) processor and a power amplifier coupled to the DPD processor and operable to provide a transmit signal at a power amplifier output. The system also includes a feedback loop coupled to the power amplifier output. The feedback loop comprises an adaptive fractional delay filter, a delay estimator coupled to the adaptive fractional delay filter, and a DPD coefficient estimator coupled to the delay estimator.

An analog-based architecture is used to produce tap spacings in an n-tap fractionally-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve fractionally spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the fractionally spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.

A signal receiver circuit may include: a receiver suitable for generating a received signal based on comparison of an input signal with a reference voltage during a normal operation and based on comparison of the input signal with a target voltage during a training operation; a compensator suitable for applying a weight to the received signal to compensate for the input signal; and a weight adjuster suitable for adjusting the weight based on a level of the received signal during the training operation, wherein during the training operation, the input signal toggles between first and second levels, and the receiver is enabled when the input signal is at the first level.

Various embodiments described herein provide for data communications using decision feedback equalization (DFE) for electro-magnetic interference (EMI) cancellation in a received signal, such as a signal received over a data communication medium and at a receiver of a communication system. In particular, some embodiments use a DFE and a feed-forward equalizer (FFE) to equalize a signal received by a first physical layer device from a second physical layer device over a data communication medium, and to operate as a narrowband notch filter to cancel EMI from the received signal.