Some embodiments include a method of forming an integrated assembly. A first stack is formed over a conductive structure. The first stack includes a second layer between first and third layers. The first and third layers are conductive. A first opening is formed through the first stack. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. The second stack has alternating first and second levels. A second opening is formed through the second stack and through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack, through the third layer, and to the second layer. The second layer is removed, forming a conduit. Second semiconductor material is formed within the conduit. Dopant is out-diffused from the second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.

Some embodiments include a method of forming an integrated assembly. A first stack is formed over a conductive structure. The first stack includes a second layer between first and third layers. The first and third layers are conductive. A first opening is formed through the first stack. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. The second stack has alternating first and second levels. A second opening is formed through the second stack and through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack, through the third layer, and to the second layer. The second layer is removed, forming a conduit. Second semiconductor material is formed within the conduit. Dopant is out-diffused from the second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.

In one embodiment that provides a technology in which process complication is suppressed and selective pattern film formation is performed, a method MT for processing a wafer W is provided, the wafer W includes a metal portion 61, an insulating portion 62, and a main surface 6, and a surface 61a of the metal portion 61 and a surface 62a of the insulating portion 62 are exposed on the main surface 6 side, the method MT includes: a step S1 of accommodating the wafer W in a processing chamber 4 of a plasma processing apparatus 10; a step S2 of starting supplying O2 gas into the processing chamber 4; and a step S3 of generating a plasma in the processing chamber 4 by the gas in the processing chamber 4 containing a SiF4 gas by supplying the SiF4 gas and plasma generation high-frequency power into the processing chamber 4, the plasma generated in the step S3 contains deposition species and etching species, and, in the plasma generated in the step S3, a proportion occupied by the etching species is greater than a proportion occupied by the deposition species.

Some embodiments include a method of forming an integrated assembly. A first stack is formed over a conductive structure. The first stack includes a second layer between first and third layers. The first and third layers are conductive. A first opening is formed through the first stack. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. The second stack has alternating first and second levels. A second opening is formed through the second stack and through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack, through the third layer, and to the second layer. The second layer is removed, forming a conduit. Second semiconductor material is formed within the conduit. Dopant is out-diffused from the second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.

A method for forming sequencing flow cells can include providing a semiconductor wafer covered with a dielectric layer, and forming a patterned layer on the dielectric layer. The patterned layer has a differential surface that includes alternating first surface regions and second surface regions. The method can also include attaching a cover wafer to the semiconductor wafer to form a composite wafer structure including a plurality of flow cells. The composite wafer structure can then be singulated to form a plurality of dies. Each die forms a sequencing flow cell. The sequencing flow cell can include a flow channel between a portion of the patterned layer and a portion of the cover wafer, an inlet, and an outlet. Further, the method can include functionalizing the sequencing flow cell to create differential surfaces.

There is provided a technique that includes: (a) providing a substrate having a film containing a predetermined element, oxygen and carbon formed on a surface of the substrate; and (b) modifying at least a surface of the film by supplying a carbon-free fluorine-based gas to the substrate under a condition in which etching of the film does not occur.

A method for forming sequencing flow cells can include providing a semiconductor wafer covered with a dielectric layer, and forming a patterned layer on the dielectric layer. The patterned layer has a differential surface that includes alternating first surface regions and second surface regions. The method can also include attaching a cover wafer to the semiconductor wafer to form a composite wafer structure including a plurality of flow cells. The composite wafer structure can then be singulated to form a plurality of dies. Each die forms a sequencing flow cell. The sequencing flow cell can include a flow channel between a portion of the patterned layer and a portion of the cover wafer, an inlet, and an outlet. Further, the method can include functionalizing the sequencing flow cell to create differential surfaces.

Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

In a semiconductor device, an insulating film is disposed between an upper surface of a substrate and a floating gate of a flash memory, a first oxide film is disposed directly above the floating gate, a silicon nitride film is disposed on an upper surface of the first oxide film, and a second oxide film made of silicon oxide film is disposed on an upper surface of the silicon nitride film.

A semiconductor device includes: a protruding conductive structure that protrudes to a height from a first surface of the semiconductor device; and a first passivation layer, the first passivation layer overlaying the protruding conductive structure by a first thickness, the first passivation layer overlaying the first surface by a second thickness greater than the first thickness, wherein the first passivation layer is planar at a top surface over the first thickness and the second thickness.