A semiconductor device includes: a protruding conductive structure that protrudes to a height from a first surface of the semiconductor device; and a first passivation layer, the first passivation layer overlaying the protruding conductive structure by a first thickness, the first passivation layer overlaying the first surface by a second thickness greater than the first thickness, wherein the first passivation layer is planar at a top surface over the first thickness and the second thickness.

Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate.

A semiconductor device includes: at least one gate structure comprising a gate electrode over a substrate, the gate electrode comprising a conductive material; and a first dielectric layer disposed along one or more side wall of the at least one gate structure, the first dielectric layer comprising fluorine doped silicon oxycarbonitride or fluorine doped silicon oxycarbide.

Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

A method for forming a semiconductor device includes steps of: forming at least one gate structure comprising a gate electrode over a substrate, and forming a first dielectric layer of a first dielectric material along a side wall of the at least one gate structure. The first dielectric layer of the first dielectric material includes fluorine doped silicon oxycarbonitride with a doping concentration of fluorine. The dielectric constant of the first dielectric layer is adjusted through the doping concentration of fluorine.

In one embodiment that provides a technology in which process complication is suppressed and selective pattern film formation is performed, a method MT for processing a wafer W is provided, the wafer W includes a metal portion 61, an insulating portion 62, and a main surface 6, and a surface 61a of the metal portion 61 and a surface 62a of the insulating portion 62 are exposed on the main surface 6 side, the method MT includes: a step S1 of accommodating the wafer W in a processing chamber 4 of a plasma processing apparatus 10; a step S2 of starting supplying O2 gas into the processing chamber 4; and a step S3 of generating a plasma in the processing chamber 4 by the gas in the processing chamber 4 containing a SiF4 gas by supplying the SiF4 gas and plasma generation high-frequency power into the processing chamber 4, the plasma generated in the step S3 contains deposition species and etching species, and, in the plasma generated in the step S3, a proportion occupied by the etching species is greater than a proportion occupied by the deposition species.

A film forming method for a target object including a main surface and grooves formed in the main surface, includes a step of supplying of a first gas into the processing chamber, and a step of supplying a second gas and a high frequency power for plasma generation into the processing chamber to generate in the processing chamber a plasma of a gas including the second gas in the processing chamber. The first gas contains an oxidizing agent that does not include a hydrogen atom. The second gas contains a compound that includes one or more silicon atoms and one or more fluorine atoms and does not include a hydrogen atom. A film containing silicon and oxygen is selectively formed on the main surface of the target object except the grooves.

In a semiconductor device, an insulating film is disposed between an upper surface of a substrate and a floating gate of a flash memory, a first oxide film is disposed directly above the floating gate, a silicon nitride film is disposed on an upper surface of the first oxide film, and a second oxide film made of silicon oxide film is disposed on an upper surface of the silicon nitride film.

Various embodiments include methods to produce low dielectric-constant (low-k) films. In one embodiment, alternating ALD cycles and dopant materials are used to generate a new family of silicon low-k materials. Specifically, these materials were developed to fill high-aspect-ratio structures with re-entrant features. However, such films are also useful in blanket applications where conformal nanolaminates are applicable. Various embodiments also disclose SiOF as well as SiOCF, SiONF, GeOCF, and GeOF. Analogous films may include halide derivatives with iodine and bromine (e.g., replace F with I or Br). Other methods, chemistries, and techniques are disclosed.