A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.

A manufacturing method of a silicon carbide semiconductor device may include: forming a gate insulating film on a silicon carbide substrate; and forming a gate electrode on the gate insulating film. The forming of the gate insulating film may include forming an oxide film on the silicon carbide substrate by thermally oxidizing the silicon carbide substrate under a nitrogen atmosphere.

The present disclosure describes an interconnect structure and a method forming the same. The interconnect structure can include a substrate, a layer of conductive material over the substrate, a metallic capping layer over the layer of conductive material, a layer of insulating material over top and side surfaces of the metallic capping layer, and a layer of trench conductor formed in the layer of insulating material and the metallic capping layer.

The present application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a semiconductor substrate, a heterojunction structure, a cap layer, a first passivation layer and a second passivation layer disposed from bottom to up; a trench penetrating through the first passivation layer and the second passivation layer; and a P-type semiconductor layer located at least on an inner wall of the trench. After a part of the second passivation layer is dry etched to form the trench, the first passivation layer can be used for etching endpoint detection to avoid over etching. A part of the first passivation layer exposed by the trench of the second passivation layer can be removed by wet etching. When the exposed part of the first passivation layer is removed by the wet etching, due to the cap layer has extremely high stability, after the exposed part of the first passivation layer is removed by the wet etching, the cap layer will not be damaged. The non-damaged cap layer can effectively reduce surface defects of the heterojunction structure to decrease a probability of electrons being trapped by the defects, thereby weakening a current collapse effect and reducing a dynamic on-resistance.

A surface treatment method for the substrate surface including two or more regions, the method including reacting a compound having the formula R.sup.1—P(═O)(OR.sup.2)(OR.sup.3), a basic nitrogen-containing compound, and the regions with each other such that a water contact angle on the metal region is greater by 10° or more with respect to a water contact angle on an insulator region close to the metal region. In compound (P-1), R.sup.1 is an alkyl group, an alkoxy group, a fluorinated alkyl group or an optionally substituted aromatic hydrocarbon group and R.sup.2 and R.sup.3 are each independently a hydrogen atom, an alkyl group, a fluorinated alkyl group or an optionally substituted aromatic hydrocarbon group.

Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer. Specifically, the substrate may include a porous portion, which is usually aligned with the metal layer, with or without a rare earth oxide layer in between.

A method and apparatus are for controlling stress variation in a material layer formed via pulsed DC physical vapour deposition. The method includes the steps of providing a chamber having a target from which the material layer is formed and a substrate upon which the material layer is formable, and subsequently introducing a gas within the chamber. The method further includes generating a plasma within the chamber and applying a first magnetic field proximate the target to substantially localise the plasma adjacent the target. An RF bias is applied to the substrate to attract gas ions from the plasma toward the substrate and a second magnetic field is applied proximate the substrate to steer gas ions from the plasma to selective regions upon the material layer formed on the substrate.

Provided is an electronic device including a lower material film, an upper material film on the lower material film, a two-dimensional electron gas between the lower material film and the upper material film, a source electrode on the upper material film, a drain electrode on the upper material film, and a gate electrode on the upper material film, wherein the upper material film includes a first portion in contact with the source electrode, a second portion in contact with the gate electrode, and a third portion in contact with the drain electrode, wherein a thickness of the second portion of the upper material film is greater than a thickness of the first portion of the upper material film and a thickness of the third portion of the upper material film, wherein the voltage drop and the threshold voltage are adjusted by adjusting the thicknesses of the first to third portions of the upper material film.