A film forming method includes: preparing a substrate having a metal layer formed on a surface of a first region and an insulating layer formed on a surface of a second region, wherein the metal layer is formed of a first metal; forming a self-assembled film on a surface of the metal layer by supplying a source gas of the self-assembled film; after forming the self-assembled film, forming an oxide film of a second metal on the insulating layer through an atomic layer deposition method by repeating a supply of a precursor gas containing the second metal and a supply of an oxidizing gas; and reducing an oxide film of the first metal formed on a surface of the first metal by supplying a reducing gas after the supply of the oxidizing gas and before the supply of the precursor gas.

The present disclosure describes epitaxial oxide high electron mobility transistors (HEMTs). In some embodiments, a HEMT comprises: a substrate; a template layer on the substrate; a first epitaxial semiconductor layer on the template layer; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer. The template layer can comprise crystalline metallic Al(111). The first epitaxial semiconductor layer can comprise (Al.sub.xGa.sub.1-x).sub.yO.sub.z, wherein 0≤x≤1, 1≤y≤3, and 2≤z≤4, wherein the (Al.sub.xGa.sub.1-x).sub.yO.sub.z comprises a Pna21 space group, and wherein the (Al.sub.xGa.sub.1-x).sub.yO.sub.z comprises a first conductivity type formed via polarization. The second epitaxial semiconductor layer can comprise a second oxide material.

The present disclosure describes an interconnect structure and a method forming the same. The interconnect structure can include a substrate, a layer of conductive material over the substrate, a metallic capping layer over the layer of conductive material, a layer of insulating material over top and side surfaces of the metallic capping layer, and a layer of trench conductor formed in the layer of insulating material and the metallic capping layer.

A method for manufacturing a semiconductor device is provided. The method includes the following. A substrate is provided. A stacked structure is formed on the substrate. The stacked structure includes first material layers and gate layers that are alternatively stacked. The stacked structure includes a giant block (GB) region and a stair-step region. A third material layer is formed on an upper surface of the GB region and an upper surface of the stair-step region. A fourth material layer filling the stair-step region and covering the GB region is formed. At least one contact structure is located in the stair-step region. Each of the at least one contact structure penetrates the third material layer and is connected with a respective one of the gate layers.

Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration, the first nitrogen concentration to a second nitrogen concentration, and/or the first number of nitrogen-nitrogen bonds to a second number of nitrogen-nitrogen bonds, each of which minimizes accumulation of copper vacancies at the interface.

Embodiments described and discussed herein provide methods for selectively depositing a metal oxides on a substrate. In one or more embodiments, methods for forming a metal oxide material includes positioning a substrate within a processing chamber, where the substrate has passivated and non-passivated surfaces, exposing the substrate to a first metal alkoxide precursor to selectively deposit a first metal oxide layer on or over the non-passivated surface, and exposing the substrate to a second metal alkoxide precursor to selectively deposit a second metal oxide layer on the first metal oxide layer. The method also includes sequentially repeating exposing the substrate to the first and second metal alkoxide precursors to produce a laminate film containing alternating layers of the first and second metal oxide layers. Each of the first and second metal alkoxide precursors contains a different metal selected from titanium, zirconium, hafnium, aluminum, or lanthanum.

A method includes forming a 2-D material semiconductor layer over a substrate; forming source/drain electrodes covering opposite sides of the 2-D material semiconductor layer, while leaving a portion of the 2-D material semiconductor layer exposed by the source/drain electrodes; forming a first gate dielectric layer over the portion of the 2-D material semiconductor layer by using a physical deposition process; forming a second gate dielectric layer over the first gate dielectric layer by using a chemical deposition process, in which a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer; and forming a gate electrode over the second gate dielectric layer.

A semiconductor structure includes a first dielectric layer, a first conductive feature, a second conductive feature, a first etch stop layer, and a conductive via. The first conductive feature and the second conductive feature are embedded in the first dielectric layer. The first etch stop layer is disposed over the dielectric layer. The conductive via is surrounded by the first etch stop layer and electrically connected to the first conductive feature, in which the conductive via is in contact with a top surface of the first etch stop layer.

A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

A semiconductor memory device includes a gate stack structure and a plurality of channel structures. The gate stack structure includes an insulating interlayer and a gate conductive layer that are alternately stacked. The plurality of channel holes is formed in the gate stack structure. The plurality of channel holes includes a fluorine-containing layer, a first blocking layer, and a charge-trapping layer. The fluorine-containing layer is formed on surfaces of the channel holes for forming the plurality of channel structures. The first blocking layer is formed on the fluorine-containing layer along the surfaces of the channel holes. The charge-trapping layer is formed on the first blocking layer along the surfaces of the channel holes.