A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. The method includes forming a dielectric etch stop layer. The dielectric etch stop is disposed on a substrate. The method also includes forming a dielectric stack on the dielectric etch stop layer. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. The method further includes forming an opening extending vertically through the dielectric stack and extending the opening through the dielectric etch stop layer. In addition, the method includes forming a selective epitaxial growth (SEG) plug at a lower portion of the opening. The SEG plug is disposed on the substrate. Moreover, the method includes forming a channel structure above and in contact with the SEG plug in the opening. The method further includes forming a memory stack comprising a plurality of interleaved dielectric layers and conductor layers by replacing the sacrificial layers in the dielectric stack with the conductor layers.

Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.

Provided are a chip matrix, a sequencing chip, and a manufacturing method thereof. The chip matrix includes: a wafer layer (111), the wafer layer (111) having cutting lines that are evenly distributed thereon; a first silicon oxide layer (112), the first silicon oxide layer (112) being made of silicon oxide and formed on an upper surface of the wafer layer (111); a transition metal oxide layer (113), the transition metal oxide layer (113) being made of transition metal oxide and formed on an upper surface of the first silicon oxide layer (112). The chip matrix has characteristics such as resistances against high temperature, high humidity and other harsh environments. Meanwhile, by changing pH, surfactant and other components of a solution containing sequences to be sequenced, a surface functional region of the chip matrix can specifically adsorb a sequence to be sequenced.

A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.

Embodiments provided herein generally relate to methods of modifying portions of layer stacks. The methods include forming deep trenches and narrow trenches, such that a desirably low voltage drop between layers is achieved. A method of forming a deep trench includes etching portions of a flowable dielectric, such that a deep metal contact is disposed below the deep trench. The deep trench is selectively etched to form a modified deep trench. A method of forming a super via includes forming a super via trench through a second layer stack of a layer superstack. The methods disclosed herein allow for decreasing the resistance, and thus the voltage drop, of features in a semiconductor layer stack.

A semiconductor device is manufactured by modifying an electromagnetic field within a deposition chamber. In embodiments in which the deposition process is a sputtering process, the electromagnetic field may be modified by adjusting a distance between a first coil and a mounting platform. In other embodiments, the electromagnetic field may be adjusted by applying or removing power from additional coils that are also present.

A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.

Bottom barrier free interconnects are provided. In one aspect, an interconnect structure includes: metal lines embedded in a dielectric; an interlayer dielectric (ILD) disposed over the metal lines; interconnects formed in the ILD on top of the metal lines; a barrier layer separating the interconnects from the ILD, wherein the barrier layer is absent in between the interconnects and the metal lines; and a selective capping layer disposed on the interconnects.

An array substrate, a display device, a thin film transistor, and a method for manufacturing an array substrate are disclosed. The array substrate includes a base substrate, an active layer, and a cover layer. The active layer is on the base substrate, the cover layer is on a side, away from the base substrate, of the active layer and covers the array substrate, the cover layer includes a metal conductive portion and a transparent insulating metal oxide portion, the metal conductive portion and the transparent insulating metal oxide portion include an identical metal element, and the metal conductive portion is electrically connected to the active layer.