Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. A substrate processing method includes providing a substrate containing a raised contact in a first dielectric film, and a second dielectric film on the first dielectric film, where the second dielectric film has a recessed feature with a sidewall and a bottom portion above the raised contact. The method further includes depositing a conformal film on the sidewall and on the bottom portion of the recessed feature, removing the conformal film from the bottom portion in a first anisotropic etching process, where the remaining conformal film forms a protection film on the sidewall and defines a width of the recessed feature, and forming a cavity containing the raised contact in an isotropic etching process, where a width of the cavity is greater than the width of the recessed feature.

A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, the first hard mask layer comprising a metal-containing material, forming a second hard mask layer over the first hard mask layer, and forming a first set of metal-containing spacers over the second hard mask layer. The method further includes patterning the second hard mask layer using the first set of metal-containing spacers as a mask, forming a second set of metal-containing spacers on sidewalls of the patterned second hard mask layer, and patterning the first hard mask layer using the second set of metal-containing spacers as a mask.

A selective film forming method includes: preparing a substrate including a first film having a first surface and a second film having a second surface, the second film being different from the first film; selectively adsorbing a secondary alcohol gas and/or a tertiary alcohol gas to the second surface; and selectively forming a film on the first surface by supplying at least a raw material gas.

Methods and precursors for selectively depositing a metal film on a silicon nitride surface relative to a silicon oxide surface are described. The substrate comprising both surfaces is exposed to a blocking compound to selectively block the silicon oxide surface. A metal film is then selectively deposited on the silicon nitride surface.

A method of forming an electrode on a substrate is disclosed. The method may include: contacting the substrate with a first vapor phase reactant comprising a titanium tetraiodide (TiI.sub.4) precursor; contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor; and depositing a titanium nitride layer over a surface of the substrate thereby forming the electrode; wherein the titanium nitride layer has an electrical resistivity of less than 400 μΩ-cm. Related semiconductor device structures including a titanium nitride electrode deposited by the methods of the disclosure are also provided.

A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO.sub.2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (Hf.sub.xTi.sub.1-xO.sub.2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

A method for forming multi-layer film on substrate, which includes steps (1) forming under layer film on substrate by applying under layer film material containing resin having repeating unit represented by the general formula (1) or (2) in which fluorene structure is contained, and curing the same by heat treatment, (2) forming metal oxide film on the under layer film by applying metal oxide film material selected from titanium oxide film material, zirconium oxide film material, and hafnium oxide film material, (3) forming hydrocarbon film on metal oxide film by applying hydrocarbon film material, and (4) forming silicon oxide film on the hydrocarbon film by applying silicon oxide film material. There can be provided a method for forming multi-layer film that can reduce reflectance, and useful for a patterning process with high dimensional accuracy of dry etching. ##STR00001##

The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 Å.