Methods for forming a laminate film on substrate by a plasma-enhanced cyclical deposition process are provided. The methods may include: providing a substrate into a reaction chamber, and depositing on substrate a metal oxide laminate film by alternatingly depositing a first metal oxide film and a second metal oxide film different from the first metal oxide film, wherein depositing the first metal oxide film and the second metal oxide film comprises, contacting the substrate with sequential and alternating pulses of a metal precursor and an oxygen reactive species generated by applying RF power to a reactant gas comprising at least nitrous oxide (N.sub.2O).

A method for forming a thin film structure may include providing a TiN member, forming a MoO.sub.2 thin film on the TiN member by using a first ALD (atomic layer deposition) process using ozone (O.sub.3) as a reactant, and forming a TiO.sub.2 thin film having a rutile crystal structure on the MoO.sub.2 thin film by using a second ALD process. The MoO.sub.2 thin film may have a thickness of about 10 nm or less. A TiO.sub.2 element layer may be further formed between the TiN member and the MoO.sub.2 thin film. The TiO.sub.2 element layer may have a nanodot array shape or a continuous layer structure. The TiO.sub.2 thin film may have a dielectric constant of 100 or more. The method of manufacturing a capacitor may further include forming a conductive material layer on the TiO.sub.2 thin film.

Semiconductor devices and methods of forming semiconductor devices are described. A method of forming metal silicon nitride films is disclosed. Some embodiments of the disclosure provide a process using ammonia plasma for treating a metal silicide or metal film to form a metal silicon nitride film. The ammonia plasma treatment generates NH* radicals that diffuse through the metal silicide to form a metal silicon nitride film that is substantially free of silicon nitride (SiN). The metal silicon nitride films have improved resistance relative to films deposited by thermal processes or plasma processes with a nitrogen plasma exposure.

A vertical metal-insulator-metal (MIM) capacitor is formed within multiple layers of a multi-level metal interconnect system of a chip. The vertical MIM capacitor has a first electrode, a second electrode, and a high-k capacitor dielectric material disposed therebetween. The dielectric constant of the capacitor dielectric material is greater than the dielectric constant of interlayer dielectric (ILD) material. After ILD is removed from between the vertically-oriented, interdigitated portions of the first and second electrodes, a capacitor dielectric material having a dielectric constant greater than the ILD dielectric material is disposed therebetween.

A substrate processing method includes applying a solution of a compound containing a metal oxide to a surface of a wafer to form a liquid film of the solution on the surface of the wafer, heating the liquid film at a first temperature lower than a crosslinking temperature of the compound, and irradiating the liquid film with energy rays to form a coating film containing the metal oxide on the surface, after heating the liquid film at the first temperature.

A printed circuit, a thin film transistor and manufacturing methods thereof are provided. The printed circuit includes a plurality of metal nanostructures and a metal oxide layer. The metal oxide layer is disposed on a surface of the metal nanostructures and fills a space at an intersection of the metal nanostructures. The metal oxide layer disposed on the surface of the metal nanostructures has a thickness of 0.1 nm to 10 nm.

Provided is a method for increasing pattern density of a structure using an integration scheme and perform pitch splitting at the resist level without the use of hard mandrels, the method comprising: providing a substrate having a patterned resist layer and an underlying layer comprising a silicon anti-reflective coating layer, an amorphous layer, and a target layer; performing a resist hardening process; performing a first conformal spacer deposition using an atomic layer deposition technique with an oxide, performing a spacer first reactive ion etch process and a first pull process on the first conformal layer, performing a second conformal spacer deposition using titanium oxide; performing a second spacer RIE process and a second pull process, generating a second spacer pattern; and transferring the second spacer pattern into the target layer, wherein targets include patterning uniformity, pulldown of structures, slimming of structures, aspect ratio of structures, and line width roughness.

A plasma CVD apparatus includes a plasma source connected to an alternating current power supply or two or more alternating current power supplies, configured to generate plasma; and a magnet array configured by a plurality of magnets. The plasma source has an electrode group, which is configured by arranging n electrodes (n being a positive even integer), in an order of electrode numbers. Each of the electrodes of the electrode group is connected to the alternating current power supply. An exit of a flow channel for a precursor gas is formed between adjacent electrodes of the electrode group. The magnet array is arranged so that a north pole or a south pole of each of the magnets is facing the plasma source. In the magnet array, for at least one pair of adjacent two magnets, poles facing the plasma source are arranged to be the same.

A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.

A substrate processing apparatus, including: a process chamber configured to process substrates; a substrate mounting stand installed in the process chamber and configured to support the substrates along a circumferential direction; a rotating unit configured to rotate the substrate mounting stand; a first gas supply unit configured to supply a first gas from above the substrate mounting stand; a second gas supply unit configured to supply a second gas from above the substrate mounting stand; a third gas supply unit configured to supply a cleaning gas from above the substrate mounting stand; and an elevating unit configured to maintain the substrate mounting stand at a substrate processing position while supplying the first gas and the second gas and also configured to maintain the substrate mounting stand at a cleaning position while supplying the cleaning gas.