A substrate processing method includes applying a solution of a compound containing a metal oxide to a surface of a wafer to form a liquid film of the solution on the surface of the wafer, heating the liquid film at a first temperature lower than a crosslinking temperature of the compound, and irradiating the liquid film with energy rays to form a coating film containing the metal oxide on the surface, after heating the liquid film at the first temperature.

Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW.sub.2O.sub.8) or hafnium tungstate (HfW.sub.2O.sub.8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages. Other embodiments which can employ techniques described herein will be apparent in light of this disclosure.

An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another.

A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.

Dielectric films for semiconductor devices and methods of forming. A processing method includes forming a first film of a first dielectric material on a substrate by performing a first plurality of cycles of atomic layer deposition and, thereafter, heat-treating the first film, where a thickness of the first film is below a threshold thickness needed for spontaneous polarization in the first dielectric material. The processing method further includes forming a second film of a second dielectric material on the substrate by performing a second plurality of cycles of atomic layer deposition and, thereafter, heat-treating the second film, where a thickness of the second film is greater than the thickness of the first film, and the second film is ferroelectric or antiferroelectric. The first and second dielectric materials can include at least one metal oxide, for example zirconium oxide, hafnium oxide, or a laminate or mixture thereof.

Methods are provided herein for deposition of oxide films. Oxide films may be deposited, including selective deposition of oxide thin films on a first surface of a substrate relative to a second, different surface of the same substrate. For example, an oxide thin film such as an insulating metal oxide thin film may be selectively deposited on a first surface of a substrate relative to a second, different surface of the same substrate. The second, different surface may be an organic passivation layer.

Transistors and method of forming he same include forming a fin on a bottom source/drain region having a channel region and a sacrificial region on the channel region. A gate stack is formed on sidewalls of the channel region. A gate conductor is formed in contact with the gate stack that has a top surface that meets a middle point of sidewalls of the sacrificial region. The sacrificial region is trimmed to create gaps above the gate stack. A top spacer is formed on the gate conductor having airgaps above the gate stack.

An antiferroelectric memory device includes at least one antiferroelectric memory cell. Each of the at least one antiferroelectric memory cell includes a first electrode, a second electrode and a stack containing an antiferroelectric layer and a doped semiconductor layer or a ferroelectric layer located between the first and the second electrodes.

Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure includes source and drain electrodes formed on a substrate, a gate insulating layer formed on a substrate covering the source and drain electrodes, wherein the gate insulating layer is a high-k material having a dielectric constant greater than 10, and a gate electrode formed above or below the gate insulating layer.

A process of forming an integrated circuit containing a piezoelectric thin film by forming a sol gel layer, drying in at least 1 percent relative humidity, baking starting between 100 and 225° C. increasing to between 275 and 425° C. over at least 2 minutes, and forming the piezoelectric thin film by baking the sol gel layer between 250 and 350° C. for at least 20 seconds, annealing between 650 and 750° C. for at least 60 seconds in an oxidizing ambient pressure between 700 and 1000 torr and a flow rate between 3 and 7 slm, followed by annealing between 650 and 750° C. for at least 20 seconds in a pressure between 4 and 10 torr and a flow rate of at least 5 slm, followed by ramping down the temperature.