The present disclosure describes a method of a thermal atomic layer deposition (ALD) process of depositing a ternary gallium oxide thin film, which includes gallium, a metal element other than gallium, and oxygen. The disclosed method starts with providing a reactive surface. Next, one or more ALD growth cycles are conducted. Each ALD growth cycle includes one or more first ALD sub-cycles and one or more second ALD sub-cycles. Herein, conducting each first ALD sub-cycles includes applying a pulse of a first metal precursor and a pulse of water sequentially, where the first metal precursor is a gallium compound. Conducting each second ALD sub-cycles includes applying a pulse of a second metal precursor and a pulse of water sequentially, where the second metal precursor includes the metal element other than gallium.

A semiconductor device includes a substrate, a gate structure over the substrate, and source/drain regions in the substrate and on opposite sides of the gate structure. The gate structure includes an interfacial layer, a quasi-antiferroelectric (QAFE) layer over the interfacial layer, and a gate electrode over the QAFE layer. The QAFE layer includes Hf.sub.1−xZr.sub.xO.sub.2, in which x is greater than 0.5 and is lower than 1.

A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO.sub.2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (Hf.sub.xTi.sub.1-xO.sub.2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.

Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW.sub.2O.sub.8) or hafnium tungstate (HfW.sub.2O.sub.8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages. Other embodiments which can employ techniques described herein will be apparent in light of this disclosure.

A dielectric film containing an alkaline earth metal oxide having a NaCl type crystal structure as a main component, wherein the dielectric film has a (111)-oriented columnar structure in a direction perpendicular to the surface of the dielectric film, and in a Cu—Kα X-ray diffraction chart of the dielectric film, a half width of the diffraction peak of (111) is in a range of from 0.3° to 2.0°.

Dielectric films for semiconductor devices and methods of forming. A processing method includes forming a first film of a first dielectric material on a substrate by performing a first plurality of cycles of atomic layer deposition and, thereafter, heat-treating the first film, where a thickness of the first film is below a threshold thickness needed for spontaneous polarization in the first dielectric material. The processing method further includes forming a second film of a second dielectric material on the substrate by performing a second plurality of cycles of atomic layer deposition and, thereafter, heat-treating the second film, where a thickness of the second film is greater than the thickness of the first film, and the second film is ferroelectric or antiferroelectric. The first and second dielectric materials can include at least one metal oxide, for example zirconium oxide, hafnium oxide, or a laminate or mixture thereof.

Provided is a semiconductor device A including: a first electrode 10; a second electrode 20; a semiconductor layer 30 in contact with the first electrode 10 and the second electrode 20; and a protective layer 40 configured to cover at least a part of a surface of the semiconductor layer 30, wherein the protective layer 40 includes a spinel oxide.

A semiconductor device include a substrate including a peripheral region, a first active pattern provided on the peripheral region of the substrate, the first active pattern having an upper portion including first semiconductor patterns and second semiconductor patterns which are alternately stacked, a first gate electrode intersecting the first active pattern, a pair of first source/drain patterns provided at both sides of the first gate electrode, respectively, and a first gate insulating layer disposed between the first gate electrode and the first active pattern. The first gate insulating layer includes a first insulating layer formed on the first active pattern, a second insulating layer formed on the first insulating layer, and a high-k dielectric layer formed on the second insulating layer. The first gate insulating layer contains a first dipole element including lanthanum (La), aluminum (Al), or a combination thereof.

Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure includes source and drain electrodes formed on a substrate, a gate insulating layer formed on a substrate covering the source and drain electrodes, wherein the gate insulating layer is a high-k material having a dielectric constant greater than 10, and a gate electrode formed above or below the gate insulating layer.