Exemplary semiconductor processing methods may include flowing deposition gases that may include a nitrogen-containing precursor, a silicon-containing precursor, and a carrier gas, into a substrate processing region of a substrate processing chamber. The flow rate ratio of the nitrogen-containing precursor to the silicon-containing precursor may be greater than or about 1:1. The methods may further include generating a deposition plasma from the deposition gases to form a silicon-and-nitrogen containing layer on a substrate in the substrate processing chamber. The silicon-and-nitrogen-containing layer may be treated with a treatment plasma, where the treatment plasma is formed from the carrier gas without the silicon-containing precursor. The flow rate of the carrier gas in the treatment plasma may be greater than a flow rate of the carrier gas in the deposition plasma.

A method is provided for selective film deposition on a substrate. According to one embodiment, the method includes providing a substrate containing a first material having a first surface and second material having a second surface, where the first material includes a dielectric material and the second material contains a semiconductor material or a metal-containing material that excludes a metal oxide, reacting the first surface with a reactant gas containing a hydrophobic functional group to form a hydrophobic first surface, and depositing, by gas phase deposition, a metal oxide film on the second surface, where deposition of the metal oxide film is hindered on the hydrophobic first surface.

There is provided a plasma generating device that includes a first electrode connected to a high-frequency power supply, and a second electrode to be grounded, a buffer structure configured to form a buffer chamber that accommodates the first and second electrodes wherein the first electrode and the second electrode are alternately arranged such that a number of electrodes of the first electrode and the second electrode are in an odd number of three or more in total, and wherein the second electrode is used in common for two of the first electrode being respectively adjacent to the second electrode used in common, and wherein a gas supply port that supplies gas into a process chamber is installed on a wall surface of the buffer structure.

A method for forming a semiconductor structure comprising a silicon-on-insulator layer structure with crystalline silicon oxide SiO.sub.x as the insulator material comprises: providing a crystalline silicon substrate having a substantially clean deposition surface in a vacuum chamber; heating the silicon substrate to an oxidation temperature To in the range of 550 to 1200 ° C.; supplying, while keeping the silicon substrate in the oxidation temperature, with an oxidation pressure P.sub.o in the range of 1.Math.10.sup.−8 to 1.Math.10.sup.−4 mbar in the vacuum chamber, molecular oxygen O.sub.2 into the vacuum chamber with an oxygen dose D.sub.o in the range of 0.1 to 1000 Langmuir; whereby a crystalline silicon oxide layer with a thickness of at least two molecular layers is formed within the silicon substrate, between a crystalline silicon base layer and a crystalline silicon top layer. Related semiconductor structures are described.

An object is to shorten the time for rewriting data in memory cells. A memory module includes a first memory cell, a second memory cell, a selection transistor, and a wiring WBL1. The first memory cell includes a first memory node. The second memory cell includes a second memory node. One end of the first memory cell is electrically connected to the wiring WBL1 through the selection transistor. The other end of the first memory cell is electrically connected to one end of the second memory cell. The other end of the second memory cell is electrically connected to the wiring WBL1. When the selection transistor is on, data in the first memory node is rewritten by a signal supplied through the selection transistor to the wiring WBL1. When the selection transistor is off, data in the first memory node is rewritten by a signal supplied through the second memory node to the wiring WBL1.

Methods and apparatuses for performing spacer on spacer multiple patterning schemes using an exhumable first spacer material and a complementary second spacer material. Certain embodiments involve using a tin oxide spacer material for one of the spacer materials in spacer on spacer self aligned multiple patterning.

Methods of and systems for reforming films comprising silicon nitride are disclosed. Exemplary methods include providing a substrate within a reaction chamber, forming activated species by irradiating a reforming gas with microwave radiation, and exposing substrate to the activated species. A pressure within the reaction chamber during the step of forming activated species can be less than 50 Pa.

A method for manufacturing a semiconductor structure includes: providing a base; forming multiple discrete first mask layers on the base; forming multiple sidewall layers, in which each sidewall layer is configured to encircle one of the first mask layers, and each sidewall layer is connected to closest sidewall layers, the side walls, away from the first mask layers, of multiple connected sidewall layers define initial first vias and each of the initial first vias is provided with chamfers; removing the first mask layers, and each sidewall layer defines a second via; after removing the first mask layers, forming repair layers which are located on the side walls, away from the second vias, of the sidewall layers and fill the chamfers of the initial first vias to form first vias; and etching the base along the first vias and the second vias to form capacitor holes on the base.

Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.

Methods for plasma enhanced atomic layer deposition (PEALD) of low-κ films are described. A method of depositing a film comprises exposing a substrate to a silicon precursor having the general formula (I) ##STR00001##
wherein R.sup.1, R.sup.2, R.sup.3, R.sup.4, R.sup.5, and R.sup.6 are independently selected from hydrogen (H), substituted alkyl, or unsubstituted alkyl; purging the processing chamber of the silicon precursor; exposing the substrate to a carbon monoxide (CO) plasma to form one or more of a silicon oxycarbide (SiOC) or silicon oxycarbonitride (SiOCN) film on the substrate; and purging the processing chamber.