A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×10.sup.14 atoms/cm.sup.3 and/or germanium at a concentration of at least about 1×10.sup.19 atoms/cm.sup.3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.

A semiconductor structure and a method for forming a semiconductor structure are provided. A sacrificial gate layer is removed to form a gate trench exposing a sacrificial dielectric layer. An ion implantation is performed to a portion of a substrate covered by the sacrificial dielectric layer in the gate trench. The sacrificial dielectric layer is removed to expose the substrate from the gate trench. An interfacial layer is formed over the substrate in the gate trench. A metal gate structure is formed over the interfacial layer in the gate trench.

A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion of a first semiconductor material and a second portion of a second semiconductor material disposed over the first portion. The second semiconductor material is different from the first semiconductor material. The semiconductor device further includes a semiconductor oxide feature disposed on sidewalls of the first portion and a gate stack disposed on the fin feature. The gate stack includes an interfacial layer over a top surface and sidewalls of the second portion and a gate dielectric layer over the interfacial layer and sidewalls of the semiconductor oxide feature. A portion of the gate dielectric layer is below the interfacial layer.

A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.

A semiconductor structure and a method for forming a semiconductor structure are provided. A sacrificial gate layer is removed to form a gate trench exposing a sacrificial dielectric layer. An ion implantation is performed to a portion of a substrate covered by the sacrificial dielectric layer in the gate trench. The sacrificial dielectric layer is removed to expose the substrate from the gate trench. An interfacial layer is formed over the substrate in the gate trench. A metal gate structure is formed over the interfacial layer in the gate trench.

A semiconductor device includes at least one active pattern on a substrate, at least one gate electrode intersecting the at least one active pattern, source/drain regions on the at least one active pattern, the source/drain regions being on opposite sides of the at least one gate electrode, and a barrier layer between at least one of the source/drain regions and the at least one active pattern, the barrier layer being at least on bottoms of the source/drain regions and including oxygen.

A method for fabricating a high-voltage (HV) transistor is provided. The method includes providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures. Further, a hydrogen annealing process is performed over the recess. A sacrificial dielectric layer is formed on the recess. The sacrificial dielectric layer is removed, wherein a portion of the first and second isolation structures is also removed. A gate oxide layer is formed in the recess between the first and second isolation structures after the hydrogen annealing process.

A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.

A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space. Fluorine is implanted into the gate sidewall spacers and the fin after forming the high-k gate dielectric layer by performing a second fluorine implantation.

A coating liquid for forming an oxide, the coating liquid including: A element, which is at least one alkaline earth metal; and B element, which is at least one selected from the group consisting of gallium (Ga), scandium (Sc), yttrium (Y), and lanthanoid, wherein when a total of concentrations of the A element is denoted by C.sub.A mg/L and a total of concentrations of the B element is denoted by C.sub.B mg/L, a total of concentrations of sodium (Na) and potassium (K) in the coating liquid is (C.sub.A+C.sub.B)/10.sup.3 mg/L or less and a total of concentrations of chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), and copper (Cu) in the coating liquid is (C.sub.A+C.sub.B)/10.sup.3 mg/L or less.