METHOD FOR FABRICATING HIGH-VOLTAGE (HV) TRANSISTOR

Abstract

A method for fabricating a high-voltage (HV) transistor is provided. The method includes providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures. Further, a hydrogen annealing process is performed over the recess. A sacrificial dielectric layer is formed on the recess. The sacrificial dielectric layer is removed, wherein a portion of the first and second isolation structures is also removed. A gate oxide layer is formed in the recess between the first and second isolation structures after the hydrogen annealing process.

Claims

1. A method for fabricating a high-voltage (HV) transistor, comprising: providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures; performing a hydrogen annealing process over the recess; forming a sacrificial dielectric layer on the recess; removing the sacrificial dielectric layer, wherein a portion of the first and second isolation structures is also removed; and forming a gate oxide layer in the recess between the first and second isolation structures after the hydrogen annealing process.

2. The method of claim 1, wherein the hydrogen annealing process is performed at a temperature in a range of 700° C. to 750° C.

3. The method of claim 1, wherein the substrate has a doped structure including: a doped well region in the substrate, wherein the first and second isolation structures are in the doped well region and the recess is also in doped well region; a first HV field doped region, in the doped well region, surrounding a bottom surface of the first trench isolation; and a second HV field doped region, in the doped well region, surrounding a bottom surface of the second trench isolation, wherein a gap is between the first HV field doped region and the second HV field doped region under the recess.

4. The method of claim 3, wherein the doped structure in the substrate id formed before the recess is formed.

5. The method of claim 1, wherein the hydrogen annealing process smooths a roughness of a bottom surface of the recess, including reducing a horn structure at bottom periphery of the recess between the substrate and the first and second isolation structures.

6. The method of claim 1, wherein the sacrificial dielectric layer is formed by performing a rapid thermal oxidation over the recess.

7. The method of claim 1, wherein the gate oxide layer is a HV gate oxide layer and a bottom of the gate oxide layer id between a top and a bottom of the first trench isolation structure or the second trench isolation structure.

8. The method of claim 1, wherein the substrate includes an epitaxial silicon layer formed on a base substrate, and the first and second trench isolation are in the epitaxial silicon layer.

9. The method of claim 1, wherein the step of forming the gate oxide layer includes a thermal oxidation layer to oxidize the substrate within the recess.

10. The method of claim 1, wherein a gas in the hydrogen annealing process is 100% of hydrogen.

11. A method for fabricating a high-voltage (HV) transistor, comprising: providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures; forming a sacrificial dielectric layer on the recess; removing the sacrificial dielectric layer, wherein a portion of the first and second isolation structures is also removed; performing a hydrogen annealing process over the recess; and forming a gate oxide layer in the recess between the first and second isolation structures after the hydrogen annealing process.

12. The method of claim 11, wherein the hydrogen annealing process is performed at a temperature in a range of 700° C. to 750° C.

13. The method of claim 11, wherein the substrate has a doped structure including: a doped well region in the substrate, wherein the first and second isolation structures are in the doped well region and the recess is also in doped well region; a first HV field doped region, in the doped well region, surrounding a bottom surface of the first trench isolation; and a second HV field doped region, in the doped well region, surrounding a bottom surface of the second trench isolation, wherein a gap is between the first HV field doped region and the second HV field doped region under the recess.

14. The method of claim 13, wherein the doped structure in the substrate id formed before the recess is formed.

15. The method of claim 11, wherein the hydrogen annealing process smooths a roughness of a bottom surface of the recess, including reducing a horn structure at bottom periphery of the recess between the substrate and the first and second isolation structures.

16. The method of claim 11, wherein the sacrificial dielectric layer is formed by performing a rapid thermal oxidation over the recess.

17. The method of claim 11, wherein the gate oxide layer is a HV gate oxide layer and a bottom of the gate oxide layer id between a top and a bottom of the first trench isolation structure or the second trench isolation structure.

18. The method of claim 11, wherein the substrate includes an epitaxial silicon layer formed on a base substrate, and the first and second trench isolation are in the epitaxial silicon layer.

19. The method of claim 11, wherein the step of forming the gate oxide layer includes a thermal oxidation layer to oxidize the substrate within the recess.

20. The method of claim 11, wherein a gas in the hydrogen annealing process is 100% of hydrogen.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to make the aforementioned and other objectives and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

[0027] FIG. 1A to FIG. 1D are drawings, schematically illustrating a method for fabricating a HV transistor as looking into, according to an embodiment of the invention.

[0028] FIG. 2A to FIG. 2E are drawings, schematically illustrating a method for fabricating a HV transistor, according to an embodiment of the invention.

[0029] FIG. 3A to FIG. 3E are drawings, schematically illustrating a method for fabricating a HV transistor, according to an embodiment of the invention.

[0030] FIG. 4 is drawing, schematically illustrating a process flow of a method for fabricating a HV transistor, according to an embodiment of the invention.

[0031] FIG. 5 is drawing, schematically illustrating a process flow of a method for fabricating a HV transistor, according to an embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

[0032] The invention is directed to a semiconductor device of HV transistor, in which the channel of the HV transistor is a recess region between two trench isolations. The surface roughness of the substrate at the recess, serving as channel, may be effectively reduced.

[0033] Multiple embodiments are provided for describing the invention but the invention is not just limited to the embodiments as provided.

[0034] FIG. 1A to FIG. 1E are drawings, schematically illustrating a method for fabricating a HV transistor as looking into, according to an embodiment of the invention.

[0035] Referring to FIG. 1A, a preliminarily structure of a HV transistor has been fabricated on the substrate 100. The trench isolations 106 are formed in the substrate 100 to define a region for subsequently forming the HV channel. The trench isolations 106 in an embodiment may protrude up from the substrate 100.

[0036] Depending on the conductive type of the HV transistor to be fabricated, various doped well and doped regions are also formed in the substrate 100. In an embodiment, a doped well 102 such as the HV P-type well (HVPW) is formed in the substrate 100. Two HV field regions 104 are formed within the doped well 102. Those various doped regions may be formed before or after the trench isolations 106 are formed.

[0037] A mask layer 108 is formed over the substate 100 but expose a region of the substrate 100 between the two trench isolations 106, in which the HV channel would be formed later. The substates 100 as exposed by the mask layer 108 is etched to have a recess 110 between the two trench isolations 106. Depending on the etchant with a etching selection ratio, the trench isolations 106 such as oxide may also be slightly etched by a certain amount. The etchant for the etching process has higher etching selection to silicon. The space of the recess 110 is used to form the HV gate insulation layer, the surface portion of the substrate 100 at the recess is also preserved to form the HV channel in operation.

[0038] Usually, the etching process would cause roughness at the recess surface 112, which is involved in HV channel in actual operation of HV transistor. The roughness at the recess surface 112 may reduce the performance of the HV channel and need to be reduced.

[0039] Referring to FIG. 1B, to reduce the surface roughness, a thermal oxidation is performed over the recess 110 to form a sacrificial dielectric layer 114, such as sacrificial oxide layer, at least oxidizing the recess surface 112. The sacrificial dielectric layer 114 may preliminarily reduce the roughness of the recess surface 114 of the substrate 100 between the trench isolations 106.

[0040] Referring to FIG. 1C, the sacrificial dielectric layer 114 is removed by etching process. In addition, the etching process may also etch trench isolations 106 to control the protruding portion 116 of the trench isolations 106 protruding from the substrate 100. As a result, the total depth of the recess 110 is corresponding to the thickness of a HV gate insulation layer 118 as to be formed in FIG. 1D.

[0041] Referring to 1D, the HV gate insulation layer 118 is formed by rapid thermal isolation process in an example to fill the space of the recess 110.

[0042] The invention has looked into the structure at the recess surface 112 according to the fabrication flow in FIG. 1A to FIG. 1D. Although the surface roughness may be reduced by forming the sacrificial dielectric layer 114 in FIG. 1B, the defect of silicon horn 112 has been observed at the edge region 120 of the substrate 100 at the recess surface 112, which is also interfacing with the trench isolations 106. This silicon horn 122 may also reduce the performance of the HV channel, since the HV channel under the HV gate insulation layer 118 would include the silicon horn 122.

[0043] After looking into the issue above, in an embodiment, the invention propose the further modification to at least further reduce the silicon horn 122.

[0044] FIG. 2A to FIG. 2E are drawings, schematically illustrating a method for fabricating a HV transistor, according to an embodiment of the invention. Referring to FIG. 2A, it is the same as the preliminary structure in FIG. 1A. The same reference numbers represent the same elements and the descriptions are omitted here. However, as noted, the recess surface 112 of the recess 110 is from the silicon material being etched.

[0045] The recess surface 112 has the roughness need to be more efficiently removed.

[0046] Referring to FIG. 2B, a hydrogen annealing process 200 is performed over the recess 110 on the recess surface 112. The roughness at the recess surface 112 may be reduced due to silicon migration under the hydrogen annealing process 200. In an embodiment, the hydrogen annealing process 200 may use the pure hydrogen at a temperature in a range of 700° C. to 750° C. In addition, the operation duration may be few minutes and the pressure may be properly applied.

[0047] Referring FIG. 2C, to further reduce the surface roughness, a thermal oxidation is performed over the recess 110 to form a sacrificial dielectric layer 114, such as sacrificial oxide layer, at least oxidizing the recess surface 112. The sacrificial dielectric layer 114 may preliminarily reduce the roughness of the recess surface 114 of the substrate 100 between the trench isolations 106.

[0048] Referring to FIG. 2D, the sacrificial dielectric layer 114 is removed by etching process. In addition, the etching process may also etch trench isolations 106 to control the protruding portion 116 of the trench isolations 106 protruding from the substrate 100. As a result, the total depth of the recess 110 is corresponding to the thickness of a HV gate insulation layer 118 as to be formed in FIG. 2E.

[0049] Referring to FIG. 2E, the HV gate insulation layer 118 is formed by rapid thermal isolation process in an example to fill the space of the recess 110.

[0050] As noted, the HV gate insulation layer 118 is interfacing with the recess portion of the substrate 100 between the trench isolations 106. The hydrogen annealing process 200 for silicon migration in FIG. 2B has been performed. As a result, the interface surface between the HV gate insulation layer 118 and the substrate 100 is at smooth condition. In addition, the silicon horn 120 as observed in FIG. 1D may be effectively reduced. As inspecting on the edge region 220 of the substrate 100 in the recess 110, the silicon horn is substantially reduced while comparing with the structure at the edge region 120 of FIG. 1D. The HV channel under the HV gate insulation layer 118 gets a smooth path in better condition for the channel current and the performance of HV channel may be improved.

[0051] The subsequent processes to complete the HV transistor may be taken based on the known processes, according to the structure at FIG. 2D. The further descriptions are omitted.

[0052] With the same aspect, the procedure in FIG. 2A to FIG. 2E may be modified. FIG. 3A to FIG. 3E are drawings, schematically illustrating a method for fabricating a HV transistor, according to an embodiment of the invention.

[0053] Referring to FIG. 3A, it is similar to FIG. 2A and the descriptions are omitted here.

[0054] Referring to FIG. 3B, it may be noted that the hydrogen annealing process 200 as described in FIG. 2B is not performed yet. However likewise to FIG. 2C, to reduce the surface roughness, a thermal oxidation is performed over the recess 110 to form a sacrificial dielectric layer 114, such as sacrificial oxide layer, at least oxidizing the recess surface 112. The sacrificial dielectric layer 114 may preliminarily reduce the roughness of the recess surface 114 of the substrate 100 between the trench isolations 106.

[0055] Referring to FIG. 3C, likewise to FIG. 2D, the sacrificial dielectric layer 114 is removed by etching process. In addition, the etching process may also etch trench isolations 106 to control the protruding portion 116 of the trench isolations 106 protruding from the substrate 100. As a result, the total depth of the recess 110 is corresponding to the thickness of a HV gate insulation layer 118.

[0056] Referring to FIG. 3D, as noted, the hydrogen annealing process 200 is performed over the recess 110 on the recess bottom surface. The roughness at the recess bottom surface may be reduced due to silicon migration under the hydrogen annealing process 200. In an embodiment, the hydrogen annealing process 200 may use the pure hydrogen at a temperature in a range of 700° C. to 750° C. In addition, the operation duration may be few minutes and the pressure may be properly applied.

[0057] Referring to FIG. 3E, after the hydrogen annealing process 200, the HV gate insulation layer 118 is formed by rapid thermal isolation process in an example to fill the space of the recess 110.

[0058] As noted, in the embodiment, the HV gate insulation layer 118 is interfacing with the recess portion of the substrate 100 between the trench isolations 106. The hydrogen annealing process 200 for silicon migration in FIG. 3D are performed after the sacrificial dielectric layer 114 is formed and removed to preliminarily reduce the surface roughness for the HV channel. However, the hydrogen annealing process 200 indeed improve the reduction of surface roughness. As a result, the interface surface between the HV gate insulation layer 118 and the substrate 100 is at smooth condition. In addition, the silicon horn 120 as observed in FIG. 1D may be effectively reduced. As inspecting on the edge region 220 of the substrate 100 in the recess 110, the silicon horn is substantially reduced while comparing with structure in the edge region 120 of FIG. 1D. The HV channel under the HV gate insulation layer 118 gets a smooth path in better condition for the channel current and the performance of HV channel may be improved.

[0059] FIG. 4 is drawing, schematically illustrating a process flow of a method for fabricating a HV transistor, according to an embodiment of the invention. Referring to FIG. 4, the fabrication procedure for fabricating a HV transistor according to the procedure in FIG. 2A to FIG. 2E may include multiples steps. In step S100, corresponding to FIG. 2A, a HV silicon recess 110 corresponding to HV channel may be formed based on a semi-finished structure. In step S102, the hydrogen annealing process 200 as referring to FIG. 2B is performed over the recess 110. In step S104, as also referring to FIG. 2C, the sacrificial (SAC) dielectric layer 114, such as SAC oxide (OX), is formed on the recess 110. In step S106, as also referring to FIG. 2D, the SAC dielectric layer 114 is removed (REM). In step S108, as also referring to FIG. 2E, the HV gate insulation layer 118, such as HV gate oxide layer (HVGOX), is formed to fill the recess 110.

[0060] Alternatively, FIG. 5 is drawing, schematically illustrating a process flow of a method for fabricating a HV transistor, according to an embodiment of the invention. Referring to FIG. 5, the fabrication procedure for fabricating a HV transistor according to the procedure in FIG. 3A to FIG. 3E may include multiples steps. In step S200, corresponding to FIG. 3A, a HV silicon recess 110 corresponding to HV channel may be formed based on a semi-finished structure. In step S202, as also referring to FIG. 3B, the SAC dielectric layer 114, such as SAC oxide (OX), is formed on the recess 110. In step S204, as also referring to FIG. 3C, the SAC dielectric layer 114 is removed (REM). In step S206, as also referring to FIG. 3D, the hydrogen annealing process 200 is performed over the recess 110. In step S208, as also referring to FIG. 3E, the HV gate insulation layer 118, such as HV gate oxide layer (HVGOX), is formed to fill the recess 110.

[0061] As to the foregoing descriptions, the hydrogen annealing process 200 is performed on the region of the substrate as preserved to be formed as HV channel. The surface roughness may be further reduced while the sacrificial dielectric layer in combination with the hydrogen annealing process 200 are performed to treat the HV channel surface. The silicon horn at the edge region of the HV channel may also be effectively reduced. The performance of the HV channel may be improved.

[0062] Although the invention is described with reference to the above embodiments, the embodiments are not intended to limit the invention. A person of ordinary skill in the art may make variations and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the invention should be subject to the appended claims.