A semiconductor device and method of forming the same are provided. The semiconductor device includes a substrate, a growth promoting region, a first gate stack, and a second gate stack. The substrate includes a first region and a second region. The growth promoting region is located in a surface of the substrate in the first region. The growth promoting region includes a first implantation species, and a surface of the substrate in the second region is free of the first implantation species. The first gate stack includes a first gate dielectric layer on the substrate in the first region. The second gate stack includes a second gate dielectric layer on the substrate in the second region.

Semiconductor devices include vertically stacked channel layers formed from a semiconductor material. A metallic interface layer is formed between metal source/drain regions and the vertically stacked channel layers. The metallic interface layer includes the semiconductor material and a metal. A gate stack is formed between and around the channel layers.

A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.

The semiconductor device includes a well region disposed in a surface layer of a semiconductor substrate, a source region and a drain region arranged separated from each other in a surface layer of the well region, a channel region disposed between the source region and the drain region, and a gate electrode disposed on the channel region via a gate insulating film containing fluorine, in which concentration of fluorine existing in a first interface, the first interface being an interface of the gate insulating film with the gate electrode, and concentration of fluorine existing in a second interface, the second interface being an interface of the gate insulating film with the channel region, are higher than concentration of fluorine existing in a middle region in the depth direction of the gate insulating film, and fluorine concentration in the first interface is higher than fluorine concentration in the second interface.

A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space. Fluorine is implanted into the gate sidewall spacers and the fin after forming the high-k gate dielectric layer by performing a second fluorine implantation.

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a gate stack, a first doped region, a second doped region, and a buried doped region. The first doped region has a first conductivity type and is located in the substrate at a first side of the gate stack. The second doped region has the first conductivity type and is located in the substrate at a second side of the gate stack. The buried doped region has the first conductivity type and is buried in the substrate, extended from the first doped region to the second doped region, and separated from the gate stack by a distance.

A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space. Fluorine is implanted into the gate sidewall spacers and the fin after forming the high-k gate dielectric layer by performing a second fluorine implantation.

The present disclosure provides a transistor, a transistor forming method thereof, and a semiconductor device. The transistor forming method comprises providing a substrate, the substrate comprising a first region for forming a source region and a second region for forming a drain region; forming a gate groove in the substrate to separate the first region and the second region, a part of the substrate along the bottom of the gate groove being used for constituting an embedded channel region of a transistor; forming a gate dielectric layer on the gate groove of the substrate to cover the embedded channel region and to extend to cover a side of the first region and a side of the second region in the gate groove; and forming a gate conductive layer on the gate dielectric layer of the substrate and in the gate groove.

An integrated circuit device includes: a substrate including active regions; a device isolation film defining the active regions; a word line arranged over the active regions and the device isolation film and extending in a first horizontal direction; and a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line, in which, in a second horizontal direction orthogonal to the first horizontal direction, a width of a second portion of the word line over the device isolation film is greater than a width of a first portion of the word line over the active regions. To manufacture the integrated circuit device, an impurity region is formed in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film, and a thickness of a portion of the impurity region is reduced.

A method is provided for operating a semiconductor device which includes an IGBT having a desaturation semiconductor structure connected to a first electrode terminal and a gate electrode terminal for controlling a desaturation channel. The method includes: applying a first gate voltage to the gate electrode terminal so that current flows through the IGBT between the first electrode terminal and a second electrode terminal and current flow through the desaturation channel is substantially blocked; applying a different second gate voltage to the gate electrode terminal so that current flows through the IGBT between the first and second electrode terminals and charge carriers flow as a desaturating current through the desaturation channel to the first electrode terminal; and applying a different third gate voltage to the gate electrode terminal so that current flow through the IGBT between the first and second electrode terminals is substantially blocked.