The present disclosure relates to a FinFET and a manufacturing method of a contact. The manufacturing method comprises steps of: sequentially generating an interlayer dielectric layer, a metal hard mask, an oxide protective cap and a tri-layer mask on a gate to form a device to be etched; photoetching the tri-layer mask to remove photoresist in a non-patterned area; performing main etch on the device to be etched after the photoetching to remove the interlayer dielectric layer in the area that is not covered by the metal hard mask, and the metal hard mask is provided with the oxide protective cap; performing ODL removal on the device to be etched after the main etch to remove remaining part of the tri-layer mask; performing oxide etch on the device to be etched after the ODL removal to remove the oxide protective cap; and generating the contact on the device after the oxide etch. The present disclosure can accurately control the critical dimensions of the contact in an X direction and a Y direction.

Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.

An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of a peripheral region of the semiconductor layer, a metal layer facing the semiconductor layer, a graphene layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the graphene layer and the semiconductor and covering the first region.

A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.

In a method for manufacturing a nitride semiconductor light-emitting element by splitting a semiconductor layer stacked substrate including a semiconductor layer stacked body with a plurality of waveguides extending along the Y-axis to fabricate a bar-shaped substrate, and splitting the bar-shaped substrate along a lengthwise split line to fabricate an individual element, the waveguide in the individual element has different widths at one end portion and the other end portion and the center line of the waveguide is located off the center of the individual element along the X-axis, and in the semiconductor layer stacked substrate including a first element forming region and a second element forming region which are adjacent to each other along the X-axis, two lengthwise split lines sandwiching the first element forming region and two lengthwise split lines sandwiching the second element forming region are misaligned along the X-axis.

A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.

A vertical field effect transistor (VFET) device and a method of manufacturing the same are provided. The method includes: (a) providing an intermediate VFET structure comprising a substrate, and fin structures, gate structures and bottom epitaxial layers on the substrate, the gate structures being formed on the fin structures, respectively, each fin structure comprising a fin and a mask thereon, and the bottom epitaxial layers; (b) filling interlayer dielectric (ILD) layers between and at sides of the gate structures; (c) forming an ILD protection layer on the ILD layers, respectively, the ILD protection layer having upper portions and lower portions, and comprising a material preventing oxide loss at the ILD layers; (d) removing the fin structures, the gate structures and the ILD protection layer above the lower portion of the ILD protection layer; (e) removing the masks of the fin structures and top portions of the gate structures so that top surfaces of the fin structures and top surfaces of the gate structures after the removing are lower than top surfaces of the ILD layers; (f) forming top spacers on the gate structures of which the top portions are removed, and top epitaxial layers on the fin structures of which the masks are removed; and (g) forming a contact structure connected to the top epitaxial layers.

Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.

A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.