In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region; forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure; removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess; forming a first interfacial layer in the first recess, the second recess, and the third recess; removing the first interfacial layer in the second recess; and forming a second interfacial layer in the second recess.

A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.

A semiconductor device includes a semiconductor part, first to fourth electrodes, first and second insulating films. The semiconductor part includes a first layer of a first conductivity type and a second layer of a second conductivity type. The first and second electrodes are provided on back and front surfaces of the semiconductor part, respectively. The second layer is provided between the first layer and the second electrode. A plurality of the third electrodes extend into the first layer through the second layer. The fourth electrode extends into the first layer from the front side of the semiconductor part and surrounds the second layer. The first insulating film electrically insulates the third electrode from the semiconductor part. The second insulating film electrically insulates the fourth electrode from the semiconductor part. The second insulating film has a first thickness greater than a second thickness of the first insulating film.

An aqueous alkaline chemical mechanical polishing composition includes a quaternary ammonium compound having a phenyl group which enables enhanced reduction of defects on silicon oxide substrates and enables good silicon oxide removal rates during chemical mechanical polishing.

The invention provides a chemical-mechanical polishing composition comprising: (a) about 3.0 wt. % to about 10 wt. % silica abrasive; (b) an anionic polymer having a weight average molecular weight of about 400 kDa to about 7000 kDa; and (c) water, wherein the polishing composition has a viscosity of at least about 1 cPs, a ratio of viscosity (cPs) to wt. % of silica abrasive of about 0.2 cPs/wt. % to about 1.5 cPs/wt. %, and a pH of about 9 to about 12. The invention additional provides a chemical-mechanical polishing composition comprising: (a) about 3.0 wt. % to about 10 wt. % silica abrasive; (b) a nonionicpolymer having a weight average molecular weight of about 300 kDa to about 7000 kDa; and (c) water, wherein the polishing composition has a viscosity of at least about 2 cPs, and a pH of about 9 to about 12. The invention also provides a method of chemically-mechanically polishing a substrate, especially a substrate comprising silicon oxide, silicon nitride, polysilicon, or combinations thereof, using said compositions.

A polishing composition according to the present invention contains zirconia particles, a selectivity improver for improving a ratio of a polishing speed for an organic material (b) to a polishing speed for a material (a) having a metal-nitrogen bond, and a dispersing medium, wherein in a particle size distribution of the zirconia particles obtained by a laser diffraction/scattering method, a diameter (D50) of the particles when a cumulative volume of the particles from a fine particle side reaches 50% of a total volume of the particles is 5 nm or more and 150 nm or less, and a pH of the polishing composition is less than 7.

A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

A semiconductor device includes a semiconductive substrate, a semiconductive fin, an isolation structure, a source/drain epitaxial structure, a first cap layer, and a second cap layer. The semiconductive fin protrudes from the semiconductive substrate. The isolation structure is over the semiconductive substrate and laterally surrounds the semiconductive fin. The source/drain epitaxial structure is over the semiconductive fin. The source/drain epitaxial structure has a rounded corner extending laterally and a top above the rounded corner. The first cap layer extends from the rounded corner of the source/drain epitaxial structure to the top of the source/drain epitaxial structure. The second cap layer covers the rounded corner and a bottom of the source/drain epitaxial structure. The first and second cap layers are made of different materials.

Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic metal oxide particles, such as ceria-coated silica; and dual chemical additives for providing the tunable oxide film removal rates and tunable SiN film removal rates. Chemical additives comprise at least one nitrogen-containing aromatic heterocyclic compound and at least one non-ionic organic molecule having more than one hydroxyl functional group organic.