In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.

The present disclosure relates to a polishing composition for a semiconductor process, which prevents polishing particles from being re-adsorbed on a wafer during a polishing process to prevent wafer defects, and improves polishing rate, selectivity, and dispersibility. In addition, when a semiconductor device is manufactured by applying the polishing composition for a semiconductor process, polarization is possible with an excellent selectivity even on a surface on which all of tungsten, a diffusion barrier layer, and an insulating layer exist.

A method includes providing a structure having source/drain electrodes and a first dielectric layer over the source/drain electrodes; forming a first etch mask covering a first area of the first dielectric layer; performing a first etching process to the first dielectric layer, resulting in first trenches over the source/drain electrodes; filling the first trenches with a second dielectric layer that has a different material than the first dielectric layer; removing the first etch mask; performing a second etching process including isotropic etching to the first area of the first dielectric layer, resulting in a second trench above a first one of the source/drain electrodes; depositing a metal layer into at least the second trench; and performing a chemical mechanical planarization (CMP) process to the metal layer.

A polishing pad includes a polyurethane, wherein the polyurethane includes a fluorinated repeating unit represented by Formula 1, wherein the number of defects on a substrate after polishing with the polishing pad and a fumed silica slurry is 40 or less; ##STR00001## wherein R.sub.11 and R.sub.12 are each independently selected from the group consisting of hydrogen, C.sub.1-C.sub.10 alkyl groups, and fluorine, with the proviso that at least one of R.sub.11 and R.sub.12 is fluorine, L is a C.sub.1-C.sub.5 alkylene group or —O—, R.sub.13 and R.sub.14 are each independently selected from the group consisting of hydrogen, C.sub.1-C.sub.10 alkyl groups, and fluorine, with the proviso that at least one of R.sub.13 and R.sub.14 is fluorine, and n and m are each independently an integer from 0 to 20, with the proviso that n and m are not simultaneously 0.

Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.

A method for forming a shallow trench isolation (STI) structure using two individual STI trench etching processes is provided. A first STI etching process forms first trenches with one or more sizes in rows along a first dimension in a silicon substrate. A first dielectric is filled in the first trenches following a first thermal oxidation forming a first liner oxide surrounding the first trenches. A second STI trench etching process forms second trenches with one or more sizes in a second dimension to define active regions separated from each other by the first trenches filled with the first dielectric material and second trenches. A second dielectric is filled in the second trenches following a second thermal oxidation forming a second liner oxide surrounding the second trenches. Active region encroachment caused by the first and second thermal oxidation is reduced by doing the two individual STI trench etching processes.

The present disclosure relates to surface modified silica, where the surface of the silica is modified by a quaternary ammonium-based polymer. Modification of the silica surface in this manner allows for production of silica particles with a high zeta potential and minimal change in particle size.

A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

A semiconductor device includes a dielectric layer having a first surface and a second surface opposite to the first surface; an active region on the first surface of the dielectric layer; a power rail under the second surface of the dielectric layer, wherein the dielectric layer is between the active region and the power rail; a spacer physically dividing the active region into a first part and a second part, the first part and the second part being conductively isolated from each other by the spacer; an intermediate layer comprising: first and second conductive segments; and wherein the spacer joins the first conductive segment and the second conductive segment, and electrically isolates the first conductive segment from the second conductive segment, wherein a join length between the first conductive segment and the spacer is equal to a join length between the second conductive segment and the spacer.