Slurry compositions for chemical mechanical polishing, chemical mechanical polishing apparatuses using the same, and methods for fabricating a semiconductor device using the same are provided. The slurry composition for chemical mechanical polishing may include polishing particles in an amount of 0.1% to 10% by weight of the slurry composition, an oxidant in an amount of 0.1% to 5% by weight of the slurry composition, a thermo-sensitive agent in an amount of 0.01% to 30% by weight of the slurry composition. The thermo-sensitive agent may include metal nanoparticles or metal oxide nanoparticles, and water, wherein the slurry composition has a pH of 1 to 8.

The present disclosure provides a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration, the method including providing a semiconductor starting wafer, the semiconductor starting wafer having a base substrate, a semiconductor layer formed over the base substrate and a buried insulating material layer formed between the semiconductor substrate and the base substrate, exposing the semiconductor starting wafer to a first oxidization process, wherein an oxide surface region is formed by oxidizing an upper surface region of the semiconductor layer, thinning the oxide surface region, exposing the semiconductor starting wafer to a second oxidization process, wherein a thickness of the oxide surface region is locally increased, and removing the oxide surface region, wherein the semiconductor layer is exposed.

This disclosure relates to a polishing composition that includes at least one abrasive; at least one nitride removal rate reducing agent, an acid or a base; and water. The at least one nitride removal rate reduce agent can include a hydrophobic portion containing a C.sub.4 to C.sub.40 hydrocarbon group; and a hydrophilic portion containing at least one group selected from the group consisting of a sulfinite group, a sulfate group, a sulfonate group, a carboxylate group, a phosphate group, and a phosphonate group; in which the hydrophobic portion and the hydrophilic portion are separated by zero to ten alkylene oxide groups. The polishing composition can have a pH of from about 2 to about 6.5.

Provided is a polishing composition which exhibits favorable storage stability and polishes a polishing object poor in chemical reactivity at a high speed. The invention is a polishing composition which contains silica having an organic acid immobilized on a surface thereof, a dihydric alcohol having a molecular weight of less than 20,000 and a pH adjusting agent, the polishing composition having a pH of 6 or less.

This disclosure relates to a polishing composition that includes at least one abrasive; at least one nitride removal rate reducing agent, an acid or a base; and water. The at least one nitride removal rate reduce agent can include a hydrophobic portion and a hydrophilic portion; in which the hydrophobic portion includes a C.sub.16 to C.sub.22 hydrocarbon group and the hydrophilic portion comprises at least one group selected from the group consisting of a phosphate group and a phosphonate group. The polishing composition has a pH of about 2 to about 6.5.

A method of forming a fully-aligned via (FAV) structure is provided. The method includes arranging conductive material adjacent to a dielectric pad and chemically deactivating a surface of the conductive material by forming a dopant-free surface-aligned monolayer (SAM) thereon. Dielectric material is deposited onto the dielectric pad aside the dopant-free SAM and the dopant-free SAM is removed from the surface of the conductive material.

To provide a technique with which in a case where sulfonic acid-modified aqueous anionic sol is used as abrasive grain, in a polishing composition for polishing an object to be polished that contains SiN, the stability of the SiN polishing rate with time can be improved, and the content of hydrogen peroxide can be decreased.

In a polishing composition having a pH of 6 or less, sulfonic acid-modified colloidal silica obtained by immobilizing sulfonic acid on surfaces of silica particles, and water are allowed to be contained, at this time, as the sulfonic acid-modified colloidal silica, the one derived from sulfonic acid-modified aqueous anionic silica sol produced by a production method including a first reaction step of obtaining a reactant by heating raw colloidal silica having a number distribution ratio of 10% or less of microparticles having a particle diameter of 40% or less relative to a volume average particle diameter based on Heywood diameter (equivalent circle diameter) as determined by image analysis using a scanning electron microscope in the presence of a silane coupling agent having a functional group chemically convertible to a sulfonic acid group; and a second reaction step of converting the functional group to a sulfonic acid group by treating the reactant is used.

Polishing compositions that can selectively and preferentially polish certain dielectric films over other dielectric films are provided herein. These polishing compositions include either cationic or anionic abrasives based on the target dielectric film to be removed and preserved. The polishing compositions utilize a novel electrostatic charge based design, where based on the charge of the abrasives and their electrostatic interaction (forces of attraction or repulsion) with the charge on the dielectric film, various material removal rates and polishing selectivities can be achieved.

A wafer level curved image sensor may include a substrate having a central region, a peripheral region, and an edge region, the peripheral region being formed between the central region and the edge region, supporting patterns formed over the substrate, first fixed patterns formed between the supporting patterns, and an image sensing chip formed over the supporting patterns. The supporting patterns and the first fixed patterns, in combination, form a planar lower surface and a concavely-curved upper surface. The image sensing chip has a curved lower surface and a curved upper surface.

A vertical memory device, including: a substrate including a cell array region and an extension region; gate electrodes stacked on each other with a plurality of levels, wherein each of the gate electrodes includes a pad, and wherein the pads disposed on the gate electrodes form at least one staircase structure on the extension region of the substrate; a channel extending in a first direction on the cell array region of the substrate through at least one of the gate electrodes; and dummy gate electrode groups disposed on the extension region of the substrate, wherein the dummy gate electrode groups includes dummy gate electrodes, wherein each of the dummy gate electrodes are spaced apart from a corresponding gate electrode among the gate electrodes stacked at a same level, wherein the dummy gate electrode groups are spaced apart from each other in a second direction.