Methods and systems for forming a structure including multiple carbon layers and structures formed using the method or system are disclosed. Exemplary methods include forming a first carbon layer and a second carbon layer, wherein a density and/or other property of the first carbon layer differs from the corresponding property of the second carbon layer.

High oxide film removal rate Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods, and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic oxide particles, such as ceria-coated silica; and a chemical additive for providing a high oxide film removal rate. The chemical additive is a gelatin molecule possessing negative and positive charges on the same molecule.

A polishing composition according to the present invention contains abrasive grains, a basic inorganic compound, an anionic water-soluble polymer, and a dispersing medium, in which a zeta potential of the abrasive grains is negative, an aspect ratio of the abrasive grains is 1.1 or less, in a particle size distribution of the abrasive grains obtained by a laser diffraction/scattering method, a ratio D90/D50 of a particle diameter D90 when an integrated particle mass reaches 90% of a total particle mass from a fine particle side to a particle diameter D50 when the integrated particle mass reaches 50% of the total particle mass from the fine particle side is more than 1.3, and the basic inorganic compound is an alkali metal salt.

The present disclosure provides a method of forming a capacitor array and a semiconductor structure. The method of forming a capacitor array includes: providing a substrate, the substrate including an array region and a non-array region, wherein a base layer and a dielectric layer are formed in the substrate, and a first barrier layer is formed between the base layer and the dielectric layer; forming, on a surface of the dielectric layer, a first array definition layer and a second array definition layer respectively corresponding to the array region and the non-array region; forming a pattern transfer layer on a surface of each of the first array definition layer and the second array definition layer; patterning the dielectric layer and the second array definition layer by using the pattern transfer layer as a mask, and forming a capacitor array located in the array region.

A method of performing a chemical mechanical planarization (CMP) process includes holding a wafer by a retainer ring attached to a carrier, pressing the wafer against a first surface of a polishing pad, the polishing pad rotating at a first speed, dispensing a slurry on the first surface of the polishing pad, and generating vibrations at the polishing pad.

A chemical mechanical polishing apparatus includes a rotatable platen to hold a polishing pad, a rotatable carrier to hold a substrate against a polishing surface of the polishing pad during a polishing process, a polishing liquid supply port to supply a polishing liquid to the polishing surface, a thermal control system including a movable nozzle to spray a medium onto the polishing surface to adjust a temperature of a zone on the polishing surface, an actuator to move the nozzle radially relative to an axis of rotation of the platen, and a controller configured to coordinate dispensing of the medium from the nozzle with motion of the nozzle across the polishing surface.

A chemical mechanical polishing apparatus includes a platen to support a polishing pad, a carrier head to hold a substrate against a polishing surface of the polishing pad, a motor to generate relative motion between the platen and the carrier head so as to polish an overlying layer on the substrate, an in-situ vibration monitoring system including a light source to emit a light beam and a sensor that receives a reflection of the light beam from a reflective surface of the polishing pad, and a controller configured to detect exposure of an underlying layer due to the polishing of the substrate based on measurements from the sensor of the in-situ pad vibration monitoring system.

A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.