The present invention relates to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, to a process for preparing the same, and to a process for preparing a semiconductor device using the same. The polishing pad according to an embodiment can achieve low hardness by comprising a polishing layer formed using a curing agent of specific components. It is possible to enhance the mechanical properties of the polishing pad, as well as to improve the surface defects appearing on the surface of a semiconductor substrate, by controlling the surface roughness reduction rate and the recovery elasticity index of the polishing pad to specific ranges. It is also possible to further enhance the polishing rate.

Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductor devices. The polishing pad may secure excellent polishing rate and within-wafer non-uniformity by controlling the physical properties such as initial load resistivity and compressive elasticity of the cushion layer and/or the laminate as defined by Equations 1 and 2: $\begin{array}{cc}L{R}_L\left(\%\right)=\frac{T1L-T2L}{T1L-T3L}\times 100& \left[\mathrm{Equation}1\right]\\ C{E}_L\left(\%\right)=\frac{T4L-}{}\end{array}$

A manufacturing method of a chip-attached substrate includes preparing a stacked substrate including multiple chips, a first substrate to which the multiple chips are temporarily bonded, and a second substrate bonded to the first substrate with the multiple chips therebetween; and separating the multiple chips bonded to the first substrate and the second substrate from the first substrate to bond the multiple chips to one surface of a third substrate including a device layer.

A semiconductor structure, a fabricating method thereof and a semiconductor device, the structure includes a substrate having a STI region and an AA, with an upper surface of the STI region lower than an upper surface of the AA; a stacked covered on the substrate; a first insulating layer covered the stacked structure, a second insulating layer covered the first insulating layer, and a third insulating layer covered the second insulating layer, over the STI region; a first insulating layer covered the stacked structure, over the AA, with an upper surface of the first insulating layer coplanar with an upper surface of the third insulating layer. The structure provides a semiconductor structure having a flat upper surface, avoiding polishing the first insulating layer over the AA to level with the first insulating layer over the STI region, greatly increasing the leakage risk, and reducing working stability of semiconductor devices.

A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.

In one embodiment, a semiconductor wafer includes a first substrate, a first insulator provided on the first substrate, and a plurality of first pads provided in the first insulator. The wafer further includes a second insulator provided on the first insulator, a plurality of second pads provided on the first pads in the second insulator, a stacked film alternately including a plurality of first insulating layers and a plurality of second insulating layers provided in the second insulator, and a second substrate provided on the second insulator. Furthermore, the first insulator and the second insulator are connected to each other between an edge face of the first insulator and an edge face of the second insulator, and the second insulator intervenes between the first insulator and the stacked film at the edge faces of the first and second insulators.

An end of polishing of a wafer is determined for each of wafers at a high accuracy. A wafer processing method includes: a first process of acquiring an initial state of a processing target surface of a wafer; a second process of forming a coating film on the wafer after the first process; a third process of polishing the processing target surface of the wafer by a polishing member based on initial polishing conditions in a state where the polishing member is in contact with the processing target surface of the wafer; a fourth process of acquiring a processed state of the processing target surface of the wafer after the third process; and a fifth process of determining an end of polishing, an insufficiency in polishing, or an excess in polishing based on the initial state and the processed state.

An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

An integrated circuit structure comprises a silicon substrate and a III-nitride (III-N) substrate over the silicon substrate. A first III-N transistor and a second III-N transistor is on the III-N substrate. An insulator structure is formed in the III-N substrate between the first III-N transistor and the second III-N, wherein the insulator structure comprises one of: a shallow trench filled with an oxide, nitride or low-K dielectric; or a first gap adjacent to the first III-N transistor and a second gap adjacent to the second III-N transistor.

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.