A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

Provided are a chemical mechanical polishing composition and a chemical mechanical polishing method that can polish a semiconductor substrate containing an electric conductor metal, such as tungsten or cobalt, flat and at high speed, and reduce post-polishing surface defects. The chemical mechanical polishing composition contains (A) silica particles having the functional group represented by general formula (1), and (B) at least one selected from the group consisting of a carboxylic acid having an unsaturated bond and a salt thereof. (1): —COO-M+ (M+ represents a monovalent cation.)

Exemplary semiconductor processing systems may include a substrate support defining an aperture therethrough. The processing systems may include a light assembly having a light source that emits an optical signal that is directed toward the aperture. The optical signal may have a high angle of incidence relative to the substrate support. The processing systems may include a photodetector aligned with an angle of reflectance of the optical signal.

The present disclosure describes an apparatus for chemical-mechanical polishing of a semiconductor wafer. Some embodiments of the present disclosure include a pad, a slurry introduction mechanism, a wafer carrier (e.g., carrying a wafer being polished by the chemical-mechanical polishing system), a pad conditioner, and a pad cooling mechanism. The pad cooling mechanism of the present disclosure may apply a liquid or gas to the pad (e.g., to an upper surface of the pad) to control the temperature of the pad as the chemical-mechanical polishing process occurs. As a result, the temperature of the pad may be maintained at a safe and operable level for an extended period of time during chemical-mechanical polishing of a wafer.

A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.

The present invention provides, in polishing an object to be polished that contains an (a) material having silicon-nitrogen bonding and (b) other materials, means that is capable of improving a ratio of a polishing speed of the (a) material to a polishing speed of the (b) materials. The present invention relates to a polishing composition used for polishing an object to be polished that contains an (a) material having silicon-nitrogen bonding and (b) other materials, the polishing composition containing: organic acid-immobilized silica; a dispersing medium; a selection ratio improver that improves a ratio of a polishing speed of the (a) material to a polishing speed of the (b) materials; and an acid, in which the selection ratio improver is organopolysiloxane having a hydrophilic group.

A method for polishing a semiconductor substrate includes the following operations. A semiconductor substrate is received. An abrasive slurry having a first temperature is dispensed to a polishing surface of a polishing pad. The semiconductor substrate is polished. The abrasive slurry have a second temperature is dispensed to the polishing surface of the polishing pad during the polishing of the semiconductor substrate. The second temperature is different from the first temperature.

Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation. Subsequently, the photopatternable dielectric material is developed to pattern the photopatternable dielectric material into a first dielectric structure which at least partially fills the opening, and to remove the photopatternable dielectric material from over the upper surface.

A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.