A semiconductor structure and a fabrication method are provided. The fabrication method includes forming a first dielectric layer on a base substrate, the first dielectric layer containing an opening exposing a surface portion of the base substrate; forming an initial gate dielectric layer on the surface portion of the base substrate and on a sidewall surface of the opening in the first dielectric layer; forming a gate dielectric layer by removing a portion of the initial gate dielectric layer from the sidewall surface of the opening, such that a top surface of the gate dielectric layer on the sidewall surface is lower than a top surface of the first dielectric layer; forming a gate electrode on the gate dielectric layer to fill the opening, a portion of the gate electrode being formed on a portion of the sidewall surface of the first dielectric layer; and forming a second dielectric layer on the gate electrode and on the first dielectric layer.

The present disclosure provides a method for preparing a vertical memory structure with air gaps. The method includes providing a substrate; forming an impurity layer at an upper portion of the substrate; forming a semiconductor stack including a lower semiconductor pattern structure filling a recess on the substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate; forming a plurality of gate electrodes surrounding a sidewall of the semiconductor stack, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction; and forming a plurality of air gap structures disposed at outer sides of the plurality of gate electrodes respectively.

A method for forming a semiconductor structure includes forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cut pattern including first and second cut features exposing portions of the respective first and second line features. In a top view, at least one of the first and second cut features is asymmetrically arranged with respect to a central axis of a corresponding first or second line feature. At least one angled ion implantation is performed to enlarge the first and second cut features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the respective first and second cut features are then removed.

In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.

A device chip manufacturing method for dividing a silicon wafer formed with devices in each of regions of a front surface partitioned by a plurality of streets includes coating the front surface of the silicon wafer with a resist film, exposing the silicon wafer by removing the resist film in regions along the streets, forming deep grooves by alternately repeating isotropic etching and coating with a passivation film, and subjecting bottom portions of the deep grooves to anisotropic etching to form division grooves, thereby dividing the silicon wafer.

Implementations of methods of singulating a plurality of die comprised in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a polymer layer over the backside metal layer and forming a groove entirely through the polymer layer and partially through a thickness of the backside metal layer. The groove may be located in a die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the polymer layer, singulating the plurality of die in the substrate by removing substrate material in the die street.

A method of manufacturing a semiconductor device is disclosed. The method includes laminating a thermally decomposable organic material on a substrate by supplying a material gas into a container in which the substrate having a first recess and a second recess, which has a wider width than a width of the first recess, are formed, fluidizing the organic material laminated on the substrate by heating the substrate to a first temperature, and removing the organic material laminated in the second recess.

Light-absorbing masks and methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits involves forming a mask above the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light-absorber species throughout the water-soluble matrix. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask with gaps and corresponding trenches in the semiconductor wafer in regions between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the patterned mask to extend the trenches and to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching.

A protective composition contains a water-soluble polyester resin including a polyvalent carboxylic acid residue and a polyvalent alcohol residue. The polyvalent carboxylic acid residue includes: a polyvalent carboxylic acid residue having a metal sulfonate group; and a naphthalene dicarboxylic acid residue. The proportion of the polyvalent carboxylic acid residue to the polyvalent carboxylic acid residue falls within the range from 25 mol % to 70 mol %. The proportion of the naphthalene dicarboxylic acid residue to the polyvalent carboxylic acid residue falls within the range from 30 mol % to 75 mol %.