A method of processing a substrate is provided. The substrate includes an etching target region and a patterned region. The patterned region is provided on the etching target region. In the method, an organic film is formed on a surface of the substrate. Subsequently, the etching target region is etched by plasma generated from a processing gas. The organic film is formed in a state that the substrate is placed in a processing space within a chamber. When the organic film is formed, a first gas containing a first organic compound is supplied toward the substrate, and then, a second gas containing a second organic compound is supplied toward the substrate. An organic compound constituting the organic film is generated by polymerization of the first organic compound and the second organic compound.

A method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant with a coolant temperature below −20° C. An etch gas is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched into the stack with respect to the patterned mask.

A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.

There is provided resist underlayer film for lithography process with high dry etching resistance, wiggling resistance, and heat resistance. Resist underlayer film-forming composition for lithography including polymer having unit structure of Formula (1): wherein A is hydroxy group-substituted C.sub.6-40 arylene group derived from polyhydroxy aromatic compound; B is C.sub.6-40 arylene group or C.sub.4-30 heterocyclic group containing nitrogen atom, oxygen atom, sulfur atom, or combination thereof; X.sup.+ is H.sup.+, NH.sub.4.sup.+, primary ammonium ion, secondary ammonium ion, tertiary ammonium ion, or quaternary ammonium ion, T is hydrogen atom, C.sub.1-10 alkyl group or C.sub.6-40 aryl group that may be substituted with halogen group, hydroxy group, nitro group, amino group, carboxylate ester group, nitrile group, or combination thereof as substituent, or C.sub.4-30 heterocyclic group containing nitrogen atom, oxygen atom, sulfur atom, or combination thereof, B and T may form C.sub.4-40 ring together with carbon atom to which they are bonded. ##STR00001##

An etching method includes a step of selectively forming deposit on a top surface of a mask disposed on a film of a substrate, a step of etching the film after the step of forming the deposit, a step of forming a layer of chemical species included in plasma of a processing gas, on the substrate, and a step of supplying ions from plasma of an inert gas to the substrate so that the chemical species react with the film.

In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

A device area and a marking area neighboring the device area over a dielectric stack are determined. The dielectric stack includes insulating material layers and sacrificial material layers arranged alternatingly over a substrate. The device area and the marking area are patterned using a same etching process to form a marking pattern having a central marking structure in a marking area and a staircase pattern in the device area. The marking pattern and the staircase pattern have a same thickness equal to a thickness of at least one insulating material layer and one sacrificial material layer, and the central marking structure divides the marking area into a first marking sub-area farther from the device area and a second marking sub-area closer to the device area. A first pattern density of the first marking sub-area is greater than or equal to a second pattern density of the second marking sub-area. A photoresist layer is formed to cover the staircase pattern and expose the marking pattern, and the photoresist layer is trimmed to expose a portion of the dielectric stack along a horizontal direction. An etching process is performed to maintain the marking pattern and remove the exposed portion of the dielectric stack and form a staircase.

The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate. The plurality of discrete gate structures and sidewall spacers are formed in the dielectric layer, and a sidewall spacer is formed on each side of each gate structure. A top portion of each gate structure and a top portion of the dielectric layer between neighboring sidewall spacers of neighboring gate structures are removed. A protective layer is formed on each of the remaining dielectric layer and the remaining gate structures. Contact holes are formed on the semiconductor substrate, between neighboring sidewall spacers, and on opposite sides of the protective layer on the remaining dielectric layer. A metal plug is formed in each contact hole.

In one embodiment, a semiconductor manufacturing apparatus includes an electrostatic chuck that includes a base and a first electrode provided on the base and is configured to electrostatically adsorb a wafer on the first electrode. The apparatus further includes a measurement module configured to measure potential of the wafer. The apparatus further includes a controller configured to adjust potential of the base based on the potential of the wafer and to adjust potential of the first electrode based on the potential of the wafer or the base, when the potential of the wafer measured by the measurement module changes.

A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.