A method may include providing a substrate having, on a first surface of the substrate, a low dielectric constant layer characterized by a layer thickness. The method may include heating the substrate to a substrate temperature in a range of 200° C. to 550° C.; and directing an ion implant treatment to the low dielectric constant layer, while the substrate temperature is in the range of 200° C. to 550° C. As such, the ion implant treatment may include implanting a low weight ion species, at an ion energy generating an implant depth equal to 40% to 175% of the layer thickness.

A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.

Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

A semiconductor device includes a substrate, a conductive layer, a nitride mask layer, a carbon mask layer and an anti-reflective coating stack. The conductive layer is disposed on the substrate. The nitride mask layer is disposed on the conductive layer, wherein the nitride mask layer has a first stress. The carbon mask layer is disposed on the nitride mask layer, wherein the carbon mask layer has a second stress and a difference between the second stress and the first stress is smaller than 200 MPa. The anti-reflective coating stack is disposed on the carbon mask layer.

A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.

In a variety of processes for forming electronic devices that use spin-on dielectric materials, properties of the spin-on dielectric materials can be enhanced by curing these materials using plasma doping. For example, hardness and Young's modulus can be increased for the cured material. Other properties may be enhanced. The plasma doping to cure the spin-on dielectric materials uses a mechanism that is a combination of plasma ion implant and high energy radiation associated with the species ionized. In addition, physical properties of the spin-on dielectric materials can be modified along a length of the spin-on dielectric materials by selection of an implant energy and dopant dose for the particular dopant used, corresponding to a selection variation with respect to length.

Methods and techniques for deposition of amorphous carbon films on a substrate are provided. In one example, the method includes depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further includes implanting a dopant or the inert species into the amorphous carbon film in a second processing region. The implant species, energy, dose & temperature in some combination may be used to enhance the hardmask hardness. The method further includes patterning the doped amorphous carbon film. The method further includes etching the underlayer.

Semiconductor devices and methods of manufacturing are provided. In some embodiments the method includes depositing an etch stop layer over a first hard mask material, the first hard mask material over a gate stack, depositing an interlayer dielectric over the etch stop layer, forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack, and treating sidewalls of the first opening with a first dopant to form a first treated region within the interlayer dielectric, a second treated region within the etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein after the treating the fourth treated region has a higher concentration of the first dopant than the first treated region.