An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

A method for forming a cavity in a semiconductor structure and an intermediate structure is provided. The method includes: (a) providing a semiconductor structure comprising: (i) a semiconductor substrate; (ii) a set of line structures on the semiconductor substrate, each line structure having a top surface and sidewalls, the line structures being separated by trenches therebetween, and (iii) an oxygen-containing dielectric material at least partially filling the trenches in-between the line structures, wherein the top surface of at least one of the line structures is at least partially exposed, and wherein the exposed part of the top surface is composed of an oxygen-free dielectric material; (b) forming a layer of TaSi.sub.x selectively onto the oxygen-free dielectric material with respect to the oxygen-containing dielectric material (c) forming the cavity by selectively removing at least a portion of the oxygen-containing dielectric material with respect to the TaSi.sub.x.

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

Techniques are provided for fabricating a semiconductor integrated circuit device which implement an interlayer dielectric (ILD) layer replacement process to replace an initial sacrificial ILD layer with a low-k ILD layer, while forming silicide or dielectric capping layers to protect source/drain contacts of field-effect transistor devices from etch damage during the ILD replacement process. For example, source/drain contact openings (e.g., trenches) are formed in a sacrificial ILD layer and metallic source/drain contacts are formed in the source/drain contact openings. Protective capping layers (e.g., metal-semiconductor alloy capping layers or dielectric capping layers) are formed on upper surfaces of the metallic source/drain contacts. The sacrificial ILD layer is removed using an etch process to etch down the sacrificial ILD layer selective to the protective capping layers, and a low-k ILD layer is formed in place of the removed sacrificial ILD layer.

An annular device is provided. The annular device includes a first transistor including a first input terminal and a second transistor including a second input terminal. The first input terminal and the second input terminal extend radially outward from the annular device, and wherein the first input terminal is aligned with the second input terminal.

Techniques are provided for fabricating a semiconductor integrated circuit device which implement an interlayer dielectric (ILD) layer replacement process to replace an initial sacrificial ILD layer with a low-k ILD layer, while forming silicide or dielectric capping layers to protect source/drain contacts of field-effect transistor devices from etch damage during the ILD replacement process. For example, source/drain contact openings (e.g., trenches) are formed in a sacrificial ILD layer and metallic source/drain contacts are formed in the source/drain contact openings. Protective capping layers (e.g., metal-semiconductor alloy capping layers or dielectric capping layers) are formed on upper surfaces of the metallic source/drain contacts. The sacrificial ILD layer is removed using an etch process to etch down the sacrificial ILD layer selective to the protective capping layers, and a low-k ILD layer is formed in place of the removed sacrificial ILD layer.

A semiconductor device and a method of forming a semiconductor device. The semiconductor device includes a first raised feature in a n-type channel field effect transistor (NFET) region on a substrate, a first doped epitaxial semiconductor material grown on the first raised feature, a first metal contact on the first doped epitaxial semiconductor material, a first metal nitride on the first metal contact, and a first ruthenium (Ru) metal plug on the first metal nitride. The device further includes a second raised feature in a p-type channel field effect transistor (PFET) region on the substrate, a second doped epitaxial semiconductor material grown on the second raised feature, a second metal contact on the second doped epitaxial semiconductor material, a second metal nitride on the second metal contact, and a second ruthenium (Ru) metal plug on the second metal nitride.

Low-resistivity dual silicide contacts for aggressively scaled semiconductor devices. A semiconductor device includes a first raised feature in a n-type channel field effect transistor (NFET) region on a substrate, a first n-type doped epitaxial semiconductor material wrapped around the first raised feature, a first metal silicide contact layer wrapped around the first n-type doped epitaxial semiconductor material, a second raised feature in p-type channel field effect transistor (PFET) region on the substrate, a second p-type epitaxial semiconductor material wrapped around the second raised feature, and a second metal silicide contact layer wrapped around the second p-type doped epitaxial semiconductor material. The first metal silicide contact layer can include a titanium silicide and the second metal silicide contact layer can include a ruthenium silicide.

Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.

A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.