A method of fabricating semiconductor device is provided. The method includes providing a substrate having a trench, plasma-ionizing a gas which comprises a deposition material precursor and a doping material precursor to respectively obtain a plasma-ionized deposition material and a plasma-ionized doping material, and depositing the plasma-ionized deposition material and the plasma-ionized doping material in the trench by applying a bias voltage to a bottom surface of the trench, wherein the bottom surface of the trench comprises a first material, and sidewalls of the trench comprise a second material different from the first material.

The present application discloses a method for manufacturing a NAND flash, comprising: step 1, sequentially form a floating gate dielectric layer and a first polysilicon layer; step 2, sequentially forming an inter-gate dielectric layer and a second polysilicon layer, wherein a first doping concentration of the second polysilicon layer is less than a target doping concentration; step 3, forming a pattern transfer mask layer; step 4, patterning the pattern transfer mask layer; step 5, performing gate etching, wherein the first and second polysilicon layers subjected to the gate etching respectively form a polysilicon floating gate and the polysilicon control gate; step 6, forming a first spacer, wherein the first spacer in a storage area fully fills a first interval area; and step 7, performing self-aligned ion implantation to increase a doping concentration of the polysilicon control gate to the target doping concentration.

A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

A method for fabricating a semiconductor device includes providing a substrate including a cell region and a core/peripheral region around the cell region, forming a gate insulating film on the substrate of the core/peripheral region, forming a first conductive film of a first conductive type on the gate insulating film, forming a diffusion blocking film within the first conductive film, the diffusion blocking film being spaced apart from the gate insulating film in a vertical direction, after forming the diffusion blocking film, forming an impurity pattern including impurities within the first conductive film, diffusing the impurities through a heat treatment process to form a second conductive film of a second conductive type and forming a metal gate electrode on the second conductive film, wherein the diffusion blocking film includes helium (He) and/or argon (Ar).

Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. The first polysilicon region is doped with a first dopant of a first conductive type and a second dopant selected from elements of group IIIA and group IVA which has an atomic weight heavier than that of silicon.

A process of forming a first mask on a first region of a metal film formed on a surface of a substrate, a process of modulating a work function of a first exposed region of the metal film, using plasma of a first process gas, a process of removing the first mask, a process of forming a second mask on a second region of the metal film, and a process of modulating the work function of a second exposed region of the metal film, using plasma of a second process gas are executed.