A process to form a HEMT can have a gate electrode layer that initially has a plurality of spaced-apart doped regions. In an embodiment, any of the spaced-apart doped regions can be formed by depositing or implanting p-type dopant atoms. After patterning, the gate electrode can include an n-type doped region over the p-type doped region. In another embodiment a barrier layer can underlie the gate electrode and include a lower film with a higher Al content and thinner than an upper film. In a further embodiment, a silicon nitride layer can be formed over the gate electrode layer and can help to provide Si atoms for the n-type doped region and increase a Mg:H ratio within the gate electrode. The HEMT can have good turn-on characteristics, low gate leakage when in the on-state, and better time-dependent breakdown as compared to a conventional HEMT.

A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.

A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.

A semiconductor device having a gate structure and a method of forming same are provided. The semiconductor device includes a substrate and a gate structure over the substrate. The substrate has a first region and a second region. The gate structure extends across an interface between the first region and the second region. The gate structure includes a first gate dielectric layer over the first region, a second gate dielectric layer over the second region, a first work function layer over the first gate dielectric layer, a barrier layer along a sidewall of the first work function layer and above the interface between the first region and the second region, and a second work function layer over the first work function layer, the barrier layer and the second gate dielectric layer. The second work function layer is in physical contact with a top surface of the first work function layer.

A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.

A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.

A semiconductor structure includes a substrate; an isolation structure over the substrate; a first fin extending from the substrate and through the isolation structure; a first source/drain structure over the first fin; a contact etch stop layer over the isolation structure and contacting a first side face of the first source/drain structure; and a first dielectric structure contacting a second side face of the first source/drain structure. The first side face and the second side face are on opposite sides of the first fin in a cross-sectional view cut along a widthwise direction of the first fin. The first dielectric structure extends higher than the first source/drain structure.

A 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, and a channel structure extending vertically through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel A first doping concentration of part of the semiconductor channel in the first portion of the channel structure is greater than a second doping concentration of part of the semiconductor channel in the second portion of the channel structure.

Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

A semiconductor device and a method of forming the semiconductor device are disclosed. A method includes forming a gate stack over a semiconductor structure. The gate stack is recessed to form a first recess. A first dielectric layer is formed along a bottom and sidewalls of the first recess, the first dielectric layer having a first etch rate. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a second etch rate, the first etch rate being higher than the second etch rate. A third dielectric layer is formed over the second dielectric layer. An etch rate of a portion of the third dielectric layer is altered. The first dielectric layer, the second dielectric layer, and the third dielectric layer are recessed to form a second recess. A capping layer is formed in the second recess.