A frame jig for manufacturing a semiconductor package includes a frame body of a rectangular shape attached to a package structure of a panel shape, wherein the frame body comprises polyphenylene sulfide.

An electrical interconnect structure includes a bond pad having a substantially planar bonding surface, and a solder enhancing structure that is disposed on the bonding surface and includes a plurality of raised spokes that are each elevated from the bonding surface. Each of the raised spokes has a lower wettability relative to a liquefied solder material than the bonding surface. Each of the raised spokes extend radially outward from a center of the solder enhancing structure.

An electronic device includes a first part, and a circuit plate including a circuit substrate, a plating film made of a plating material and being disposed on a front surface of the substrate. The plating film includes a first part region on which the first part is disposed via a first solder, and a liquid-repellent region extending along a periphery side of the first part region in a surface layer of the plating film, and having a liquid repellency greater than a liquid repellency of the plating film. The liquid-repellent region includes a resist region. The plating film includes a remaining portion between the liquid-repellent region and the front surface of the circuit substrate in a thickness direction of the plating film orthogonal to the front surface. The remaining portion is made of the plating material and is free of the oxidized plating material.

In some examples, an electronic package and methods for forming the electronic package are described. The electronic package can be formed by disposing an interposer on a surface of a substrate having a first pitch wiring density. The interposer can have a second pitch wiring density different from the first pitch wiring density. A layer of non-conductive film can be situated between the interposer and the surface of the substrate. A planarization process can be performed on a surface of the substrate. A solder resist patterning can be performed on the planarized surface the substrate. A solder reflow and coining process can be performed to form a layer of solder bumps on top of the planarized surface of the substrate. The interposer can provide bridge connection between at least two die disposed above the substrate. Solder bumps under the interposer electrically connect the substrate and the interposer.

A method for assembling an optoelectronic package assembly includes engaging a connector holder with a substrate, the connector holder defining an engagement feature and the substrate including optical waveguides, engaging a connector of a fiber array unit with the engagement feature the connector holder where the engagement feature retains the connector and where the fiber array unit includes the connector and optical fibers coupled to the connector, optically coupling the optical fibers to the optical waveguides of the substrate, heating the connector holder, the fiber array unit, the substrate, and a solder positioned between the substrate and a base substrate, where the heating is sufficient to melt the solder, and cooling the solder to couple the substrate to the base substrate.

A method of coupling a first semiconductor device to a second semiconductor device can include encapsulating solder balls on a first surface of a first substrate of the first semiconductor device with an encapsulant material. In some embodiments, the method includes removing a portion of the encapsulant material and a portion the solder balls to form a mating surface. The method can include reflowing the solder balls. In some embodiments, the method includes inserting exposed conductive pillars of the second semiconductor device into the reflowed solder balls.

An integrated substrate structure includes a redistribution film, a circuit substrate, and a plurality of conductive features. The redistribution film includes a fine redistribution circuitry, a circuit substrate is disposed over the redistribution film and includes a core layer and a coarse redistribution circuitry disposed in and on the core layer. The circuit substrate is thicker and more rigid than the redistribution film, and a layout density of the fine redistribution circuitry is denser than that of the coarse redistribution circuitry. The conductive features are interposed between the circuit substrate and the redistribution film to be connected to the fine redistribution circuitry and the coarse redistribution circuitry. A redistribution structure and manufacturing methods are also provided.

A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.

A method of manufacturing an electronic module includes supplying paste to an electronic component and/or a wiring board. The paste includes solder powder and first resin. The method includes supplying second resin to the electronic component and/or the wiring board. The method includes placing one of the electronic component and the wiring board on another. The method includes curing the second resin to form a second resin portion. The method includes heating the paste to a temperature equal to or higher than a solder melting point after the second resin portion is formed. The method includes solidifying molten solder at a temperature lower than the solder melting point to form a solder portion that bonds the electronic component and the wiring board. The method includes curing the first resin after the solder portion is formed, to form a first resin portion.

A method of fabricating a porous wafer battery comprises the steps of providing a silicon wafer comprising a plurality of pores; applying a first metallization process; applying a passivation process; applying solder balls, aligning the silicon wafer with a substance, and applying a solder reflow process. A method using a porous wafer battery comprises the steps of connecting the porous wafer battery to a plurality of sensors, a plurality of switches, and a battery management system; monitoring temperature, resistance, or current; and electrically disconnecting a non-properly functioning pore.