A chip comprises a porous wafer battery and a device. The chip further comprises a wafer containing the device and at least a portion of the porous wafer battery. The wafer comprises a silicon substrate. The silicon substrate comprises a first region and a second region. The first region comprises a plurality of pores of the porous wafer battery. The second region 345 comprises a trench to accommodate a gate electrode of the device. A method of fabrication a chip comprising the steps of providing a substrate comprising a plurality of doped regions; patterning a mask on a front surface of the substrate; applying an etching process forming the plurality of pores in the first region of the substrate and the trench in the second region of the substrate; and then removing the mask.

A porous two-wafer battery comprises a first wafer and a second wafer. Each of the first wafer and the second wafer comprises a substrate, a conductive layer, and a passivation layer. The first wafer is parallel to the second wafer. The passivation layer of the first wafer is closer to the passivation layer of the second wafer. The first wafer serves as an anode and the second wafer serves as a cathode. The substrate comprises a plurality of pores and a P+ doped region. The plurality of pores are symmetric with respect to a respective center of each of the first wafer and the second wafer. An adhesion promotion layer is between the conductive layer and a respective side wall of the plurality of pores.

A method of fabricating a porous wafer battery comprises the steps of providing a silicon wafer; forming a P+ doped region; patterning a mask; applying an etching process; removing the mask; applying a first metallization process; applying a second metallization process; applying a passivation process; and applying a back-end metallization process. A P+ doped region is introduced in the wafer. The P+ doped region can serve as an etch stop. The P+ doped region may also act as a good Ohmic contact for the back-end metallization.

A battery package comprises a plurality of porous wafer batteries and a housing enclosing the plurality of porous wafer batteries. Each of the plurality of porous wafer batteries may be a one-wafer battery or a two-wafer battery. Each pore of a plurality of pores of the one-wafer battery comprises a respective anode and a respective cathode. A first wafer of the two-wafer battery is an anode and a second wafer of the two-wafer battery is a cathode. The battery package further comprises a plurality of heating wafers and a plurality of cooling wafers. A cavity of the housing may be filled with a liquid.

A method of coupling a first semiconductor device to a second semiconductor device can include encapsulating solder balls on a first surface of a first substrate of the first semiconductor device with an encapsulant material. In some embodiments, the method includes removing a portion of the encapsulant material and a portion the solder balls to form a mating surface. The method can include reflowing the solder balls. In some embodiments, the method includes inserting exposed conductive pillars of the second semiconductor device into the reflowed solder balls.

A method of using a processing oven may include disposing at least one substrate in a chamber of the oven and activating a lamp assembly disposed above them to increase their temperature to a first temperature. A chemical vapor may be admitted into the chamber above the at least one substrate and an inert gas may be admitted into the chamber below the at least one substrate. The temperature of the at least one substrate may then be increased to a second temperature higher than the first temperature and then cooled down.

A novel packaging method for attached (SMD-type) single small-size and array type chip semiconductor components is disclosed. The configuration of circuit board(s) with double-side interconnections includes reserving two or more connection endpoints on the inner and outer layers of a double-sided circuit board, and interconnecting the circuits on the inner and outer layers by hole drilling and electroplating, such that the two or more connection endpoints on the inner layer are used as inner electrodes for connecting with a semiconductor die, whereas the two or more connection endpoints on the outer layer are used as outer electrodes for SMT soldering.

An improved interconnect substrate having high density routings for a chip package assembly, a chip package assembly having a high density substrate, and methods for fabricating the same are provided that utilize substrates having a region of high density routings disposed over a region of low density routings. In one example, a method for fabricating an interconnect substrate is provided that includes forming a high density routing region by depositing a seed layer on a top surface of a low density routing region, patterning a mask layer on the seed layer, forming a plurality of conductive posts on the seed layer, removing the mask layer and the seed layer exposed between the conductive posts, and depositing a dielectric layer between the between the conductive posts, wherein at least some of the conductive posts are electrically coupled to conductive routing comprising the low density routing region.

Methods of manufacture are described. A method includes forming a first cavity in a substrate and placing a backplane in the first cavity. At least one layer of dielectric material is formed over the substrate and the backplane. A second cavity is formed in the at least one layer of the dielectric material to expose at least a portion of a surface of the backplane. A heat conductive material is placed in the second cavity and in contact with the at least the portion of the surface of the backplane.

Panels of LED arrays and LED lighting systems are described. A panel includes a substrate having a top and a bottom surface. Multiple backplanes are embedded in the substrate, each having a top and a bottom surface. Multiple first electrically conductive structures extend at least from the top surface of each of the backplanes to the top surface of the substrate. Each of multiple LED arrays is electrically coupled to at least some of the first conductive structures. Multiple second conductive structures extend from each of the backplanes to at least the bottom surface of the substrate. At least some of the second electrically conductive structures are coupled to at least some of the first electrically conductive structures via the backplane. A thermal conductive structure is in contact with the bottom surface of each of the backplanes and extends to at least the bottom surface of the substrate.