Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes providing a substrate comprising a metal region and a dielectric region surrounding the metal region, selectively forming a cobalt-containing alloy cap layer on the metal region by exposing the substrate to a first precursor and a second precursor, the first precursor and the second precursor are selected from a group consisting of an aluminum-containing precursor, a cobalt-containing precursor, a ruthenium-containing precursor, a manganese-containing precursor, and a tungsten-containing precursor, wherein the first precursor is different from the second precursor.

An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.

A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

A method of manufacturing a contact on a semiconductor region includes a step of forming a stack of layers on lateral walls and at a bottom of an orifice (aligned with the semiconductor region) crossing a dielectric region along a longitudinal direction. The step of forming step is carried out from a first surface of the dielectric region and includes forming a polysilicon layer and a layer of a first metal in contact with the polysilicon layer. The first metal is preferably a metal selected from the group of transition metals and is well suited to forming with the polysilicon layer a metal silicide. The method further includes a step of performing thermal anneal causing a reaction between the first metal and the polysilicon layer to produce a layer of metal silicide. At least a portion of that layer of metal silicide extends in the longitudinal direction of the orifice.

A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure comprises a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.

A recessed gate structure includes a recessed structure, wherein the recessed structure comprises a substrate with the recess extending into the substrate from a topmost surface of the substrate; a conductive feature, filled in the recess of the recessed structure; a first functional layer, extending between the conductive feature and the recessed structure, and comprising a first element; a second functional layer, extending between the first functional layer and the conductive feature, and comprising a second element; and an interfacial layer, extending along an interface between the first functional layer and the second functional layer, and comprising the first element and the second element.

Integrated circuit interconnect structures including an interconnect metallization feature with a barrier material comprising a metal and a chalcogen. Introduction of the chalcogen may improve diffusion barrier properties at a given barrier material layer thickness with increasing the barrier layer thickness. A barrier material, such as TaN, may be deposited at minimal thickness, and doped with a chalcogen before or after one or more fill materials are deposited over the barrier material. During thermal processing mobile chalcogen impurities may collect within regions within the barrier material to high enough concentrations for at least a portion of the barrier material to be converted into a metal chalcogenide layer. The metal chalcogenide layer may have greater crystallinity than a remainder of the barrier layer.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Each electrically conductive layer within a subset of the electrically conductive layers includes a respective first metal layer containing an elemental metal and a respective first metal silicide layer containing a metal silicide of the elemental metal. Memory openings vertically extend through the alternating stack. Memory opening fill structures located within the memory openings can include a respective memory film and a respective vertical semiconductor channel.

Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM comprises a hydrocarbon having a formula of H—C≡C—R, wherein R is a linear alkyl chain or aryl group comprising from 1 to 20 carbon atoms or a formula of R′C═CR″, wherein R′ and R″ independently include a linear alkyl chain or aryl group comprising from 1 to 20 carbon atoms A barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

A semiconductor structure manufacturing method according to the embodiments of the present application includes the following steps of: providing a semiconductor substrate; forming a first reaction layer on the semiconductor substrate; forming a second reaction layer on the first reaction layer; and thermally reacting at least a portion of the first reaction layer with at least a portion of the second reaction layer, to form an amorphous diffusion barrier layer. This amorphous diffusion barrier layer is an amorphous body with no grain boundary therein. As a result, the diffusion path for metal atoms is cut off, thereby improving the barrier effect of the barrier layer efficiently and solving the circuit performance issue caused by metal atom diffusion.