A method of manufacturing a semiconductor device, includes: stacking a thermally-decomposable organic material on a surface of a substrate in which a recess is formed; implanting ions into a surface of the organic material stacked in the recess so as to modify the surface of the organic material and form a modified layer on the surface of the organic material; and heating the substrate to a first temperature so as to thermally decompose the organic material under the modified layer and to desorb the organic material through the modified layer so that an air gap is formed between the modified layer and the recess.

Some embodiments include a method of forming an integrated assembly. A stack of alternating first and second materials is formed over a conductive structure. The conductive structure includes a semiconductor-containing material over a metal-containing material. An opening is formed to extend through the stack and through the semiconductor-containing material, to expose the metal-containing material. The semiconductor-containing material is doped with carbon and/or with one or more metals. After the doping of the semiconductor-containing material, the second material of the stack is removed to form voids. Conductive material is formed within the voids. Insulative material is formed within the opening. Some embodiments include integrated assemblies having carbon distributed within at least a portion of a semiconductor material.

The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition.

Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.

Some embodiments include a method of forming an integrated assembly. A stack of alternating first and second materials is formed over a conductive structure. The conductive structure includes a semiconductor-containing material over a metal-containing material. An opening is formed to extend through the stack and through the semiconductor-containing material, to expose the metal-containing material. The semiconductor-containing material is doped with carbon and/or with one or more metals. After the doping of the semiconductor-containing material, the second material of the stack is removed to form voids. Conductive material is formed within the voids. Insulative material is formed within the opening. Some embodiments include integrated assemblies having carbon distributed within at least a portion of a semiconductor material.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a target layer, a plurality of metal pads, a plurality of conductive lines, a plurality of conductive plugs, an isolating liner, and a plurality of metal contacts. The semiconductor substrate has a front surface, a rear surface opposite to the front surface, and an implanted region connected to the rear surface. The target layer is disposed over the front surface. The metal pads are disposed over the target layer. The plurality of conductive lines are disposed within the semiconductor substrate and the target layer and connected to the metal pads. The conductive plugs are disposed in the implanted region. The isolating liner encircles the conductive plugs. The metal contacts are disposed over the conductive lines and the conductive plugs.

An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.

Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner. The superlattice liner may include a plurality of stacked groups of layers, each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group being constrained within a crystal lattice of adjacent base semiconductor portions. The device may also include a semiconductor layer on the superlattice liner and including a dopant constrained therein by the superlattice liner, and a conductive body within the at least one trench defining a source contact.