A method of forming a semiconductor device includes patterning a dielectric layer to form a groove and depositing a plurality of conductive layers over the dielectric layer and in the groove. The first conductive layer is a liner layer, the second conductive layer is a metal film, and the third conductive layer is a capping layer. The first conductive layer is treated with a hydrogen plasma treatment to remove impurities. The first conductive layer is also treated with a hydrogen soak treatment to remove microvoids. The third conductive layer is treated with an ammonia plasma treatment to remove impurities. The third conductive layer is also treated with a hydrogen plasma treatment to remove additional impurities. The third conductive layer is also treated with a hydrogen soak treatment to remove microvoids.

A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping.

Back end of line (BEOL) structures and methods generally includes forming at least two adjacent conductors separated by a space formed in a first dielectric material, wherein a liner layer is intermediate the first dielectric material and each of the at least two adjacent conductors. A second dielectric material in the space between the at least two adjacent conductors and in contact with the first dielectric material at a bottom surface thereof, wherein the first dielectric material is different from the second dielectric material, and wherein the first dielectric material has a nitrogen enriched surface at an interface between the first dielectric material and the second dielectric material. The nitrogen enriched surface can be formed by plasma nitridation, thermal nitridation, or laser annealing in the presence of nitrogen gas, ammonia, or a combination thereof.

An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.

A plasma processing apparatus includes: a processing chamber in which a sample is subjected to plasma treatment; a radio frequency power supply configured to supply radio frequency power that generates plasma; a sample stage on which the sample is placed; and an ultraviolet light source configured to apply an ultraviolet ray. The apparatus further includes a controller configured to control the ultraviolet light source such that before the radio frequency power is supplied into the processing chamber, a pulse-modulated ultraviolet ray is applied into the processing chamber.

A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.

A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.

Back end of line (BEOL) structures and methods generally includes forming at least two adjacent conductors separated by a space formed in a first dielectric material, wherein a liner layer is intermediate the first dielectric material and each of the at least two adjacent conductors. A second dielectric material in the space between the at least two adjacent conductors and in contact with the first dielectric material at a bottom surface thereof, wherein the first dielectric material is different from the second dielectric material, and wherein the first dielectric material has a nitrogen enriched surface at an interface between the first dielectric material and the second dielectric material. The nitrogen enriched surface can be formed by plasma nitridation, thermal nitridation, or laser annealing in the presence of nitrogen gas, ammonia, or a combination thereof.

An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer. The method also includes creating a vacuum environment around the device. After creating the vacuum environment around the device, the method includes etching through the etch stop layer to extend the opening and expose a first conductive feature. The method also includes forming a second conductive feature in the opening.