Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping.

Embodiments described herein generally relate to enable the formation of a metal gate structure with a reduced effective oxide thickness over a similar structure formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridization process is performed on a metal nitride layer in a film stack, thereby removing oxygen atoms disposed within layers of the film stack and, in some embodiments eliminating an oxygen-containing interfacial layer disposed within the film stack. As a result, an effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift. Further, the metal gate structure operates with an increased leakage current that is as little as one quarter the increase in leakage current associated with a similar metal gate structure formed via conventional techniques.

In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition.

Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

Conductive structures and method of manufacture thereof are disclosed. A barrier layer can line the first recess of a substrate. A first seed layer can be formed on the barrier layer and line a bottom of the first recess and partially line sidewalls of the recess. A first conductive material can partially fill the first recess to form a second recess. The top surface of the first conductive material can coincide with a vertical extent of the first seed layer and have a depression formed therein. A second seed layer can be formed on the barrier layer and line the second recess. A second conductive material can fill the second recess.

A semiconductor device is provided which comprises a metal interconnect structure having a metal alloy capping layer formed within a surface region of the metal interconnect structure, as well as methods for fabricating the semiconductor device. For example, a method comprises forming a metal interconnect structure in a dielectric layer, and applying a surface treatment to a surface of the metal interconnect structure to form a point defect layer in the surface of the metal interconnect structure. A metallic capping layer is then formed on the point defect layer of the metal interconnect structure, and a thermal anneal process is performed to convert the point defect layer into a metal alloy capping layer by infusion of metal atoms of the metallic capping layer into the point defect layer. The resulting metal alloy capping layer comprises an alloy of metallic materials of the metal capping layer and the metal interconnect structure.

A method is presented for forming an enlarged contact area. The method includes forming a trench for receiving a first conductive material, forming a noble metal cap over a portion of the first conductive material, forming a dielectric capping layer over the noble metal cap, etching a portion of the first conductive material to create a via anchoring structure and an undercut region exposing a bottom surface of the noble metal cap, and depositing a plurality of liners such that one liner of the plurality of liners directly contacts an entirety of the exposed bottom surface of the noble metal cap.

The present invention provides a technology capable of removing impurities remaining in a thin film when the film is formed and modifying a characteristic of the thin film according to a change in impurity concentration. There is provided a method of manufacturing a semiconductor device including: (a) repetitively supplying a plurality of gases including elements constituting a film in temporally separated pulses (in non-simultaneous manner) to form the film on the substrate; and (b) exciting a modifying gas including a reducing gas and at least one of a nitriding gas and an oxidizing gas by plasma and supplying the modifying gas excited by plasma to modify the film.

Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.