A substrate processing method is for forming a metal film on a target substrate by using a plasma. The method includes loading a target substrate having a silicon-containing layer on a surface thereof into a processing chamber which is pre-coated by a film containing a metal, introducing hydrogen gas and a gaseous compound of the metal and halogen into the processing chamber, generating a plasma, and forming a metal film on the target substrate. The method further includes performing a first reduction process of forming an atmosphere of a plasma obtained by activating hydrogen gas in the processing chamber, unloading the target substrate from the processing chamber, performing a second reduction process of forming an atmosphere of a plasma obtained by activating hydrogen gas in the processing chamber, and loading a next target substrate into the processing chamber.

An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.

An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.

Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

Disclosed are methods of preparing a semiconductor substrate having a metal seed layer for a subsequent electroplating operation. In some embodiments, the methods may include contacting the surface of the semiconductor substrate with a plasma to treat the surface by reducing metal oxides thereon and thereafter measuring a post-plasma-contact color signal from said surface, the color signal having one or more color components. The methods may then further include estimating the extent of the oxide reduction due to the plasma treatment based on the post-plasma contact color signal. In some embodiments, estimating the extent of the oxide reduction due to the plasma treatment is done based on the b* component of the post-plasma contact color signal. Also disclosed are plasma treatment apparatuses which may implement the foregoing methods.

Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers.

In one embodiment of the present disclosure, a method for electrochemical deposition on a workpiece includes (a) obtaining a workpiece including a feature; (b) depositing a first conductive layer in the feature; (c) moving the workpiece to an integrated electrochemical deposition plating tool configured for hydrogen radical H* surface treatment and electrochemical deposition; (d) treating the first conductive layer using a hydrogen radical H* surface treatment in a treatment chamber of the plating tool to produce a treated first conductive layer; and (e) maintaining the workpiece in the same plating tool and depositing a second conductive layer in the feature on the treated first conductive layer in an electrochemical deposition chamber of the plating tool.

A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.

A semiconductor device includes an interconnect structure embedded in a first metallization layer comprising a dielectric material. The interconnect structure includes a first metal material. The semiconductor device includes a first liner structure embedded in the first metallization layer. The first liner structure is extended along one or more boundaries of the interconnect structure in the first metallization layer. The first liner structure includes a second metal material reacted with one or more dopants, the second metal material being different from the first metal material.